TMC2242A/TMC2242B
PRODUCT SPECIFICATION
Table 4b. Output Data Formats and Bit Weighting for TCO = 1
Interpolation Mode (TMC2242A and TMC2242B when INT = 0 and DEC = 1)
-21
Decimation, Equal Rate Modes (and TMC2242B in unity gain interpolate mode with INT = DEC = 0)
-20 2-1 2-2 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15
Rounded LSBs as a function of RND
20
2-1
…
26
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
…
2-0
RND
2-0
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
…
…
…
…
…
…
…
…
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
SO
0r
000
001
010
011
100
101
110
111
15
15
15
15
15
15
15
15
14
14
14
14
14
14
14
14
13
13
13
13
13
13
13
13
8
8
8
8
8
8
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
SO
SO
SO
SO
SO
SO
0
0
0
0
0
0
0
0
1r
SO
0
7
6
5
4
3
2r
SO
0
0
7
6
5
4
3r
SO
0
0
0
7
6
5
4r
SO
0
0
0
0
7
6
5r
SO
0
0
0
0
0
7
6r
SO
0
0
0
0
0
7r
Notes:
1. A leading minus sign denotes the two’s complement sign bit.
2. When TCO=0, the most significant bit of the output is positive instead of negative.
3. In all operating modes except INT = 0 and DEC = 1, the gain is approximately unity. When INT = 0 and DEC = 1, the output
gain is -6 dB.
4. The "r" indicates that the trailing significant output bit has been rounded to the nearest 1/2 LSB. (Internally, the chip adds 1 to
the next lower bit, to allow the user to obtain a properly rounded output)
Table 5.TMC2242A Steady-State Output Values and Limiter Triggers (L) versus Input Data
INT = 1 or DEC = 0
INT = 0 and DEC = 1
Input
7FF
400
001
000
FFF
C00
801
TCO = 0
TCO = 1
7FFF (L)
4018
TCO = 0
TCO = 1
4008 / 4018
2008 / 2010
0008
Interpretation
+ full-scale
+1/2 scale
+1 LSB
0000 (L)
3FE7
3FF7 / 3FE7
5FF7 / 5FEF
7FF7
7FEF
0010
7FFF
0000
7FFF
0000
Zero
800F
FFF0
8007
FFF8
-1 LSB
C017
BFE8
A007 / A00F
C007 / C017
DFF8 / DFF0
BFF8 / BFE8
-1/2 scale
- full-scale
FFFF (L)
8000 (L)
7
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