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TMC2242B 参数 Datasheet PDF下载

TMC2242B图片预览
型号: TMC2242B
PDF下载: 下载PDF文件 查看货源
内容描述: 数字半带插值/抽取滤波器的12位输入/ 16位输出, 60 MHz的 [Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz]
分类和应用:
文件页数/大小: 16 页 / 188 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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PRODUCT SPECIFICATION  
TMC2242A/TMC2242B  
Description (continued)  
The filter response is flat to within ±0.01 dB from 0.00 to  
To perform decimation, the chip sets the output register  
0.22 x f , with stopband attenuation greater than 59.4 dB  
clock rate to half of the input rate. One output is then  
obtained for every two inputs.  
s
from 0.28 x f to the Nyquist frequency. The response is 6 dB  
s
down at 0.25 x f . Symmetric-coefficient filters such as the  
s
TMC2242A and TMC2242B have linear phase response.  
Full compliance with the CCIR-601 standard of 12 dB atten-  
uation at 0.25 x f is achieved by cascading two parts.  
s
For interpolation, the user should bring SYNC HIGH for at  
least one clock cycle, returning it LOW with the first desired  
input data value. When interpolating, the chip will then con-  
tinue to accept a new data input on each alternate rising edge  
of the clock. When decimating, the chip will present one out-  
put value for every two clock cycles. The user may leave  
SYNC LOW or toggle it once per rising clock edge, with  
equivalent performance.  
The TMC2242A and TMC2242B are fabricated on an  
advanced submicron CMOS process. They are available in a  
44-lead J-lead PLCC package. Performance is guaranteed  
from 0°C to 70°C.  
The output data format is two's complement if TCO is  
HIGH, inverted offset binary if LOW. The user can tailor the  
output data word width to his/her system requirements using  
the Rounding control. As shown in Table 4, the output is  
half-LSB rounded to the resolution selected by the value of  
Functional Description  
The TMC2242A and TMC2242B implement a fixed-coeffi-  
cient linear-phase Finite Impulse Response (FIR) filter of 55  
effective taps, with special rate-matching input and output  
structures to facilitate 2:1 decimation and 1:2 interpolation.  
The faster of either the input or output registers will operate  
at the guaranteed maximum clock rate (speed grade). The  
total internal pipeline latency from the input of an impulse to  
the corresponding output peak (digital group delay) is 34  
cycles; the 55-value output response begins after 7 clock  
cycles and ends after 61 cycles.  
RND . The asynchronous three-state output enable control  
2-0  
simplifies connection to a data bus with other drivers.  
Table 1. Operating Modes  
DEC INT  
TMC2242A  
Equal Rate  
Decimate  
TMC2242B  
Interpolate (0 dB)  
Decimate  
0
0
1
1
0
1
0
1
To perform interpolation, the chip slows the effective input  
register clock rate to half the output rate. It internally inserts  
zeroes between the incoming data samples to "pad" the input  
data rate to match the output rate.  
Interpolate (-6 dB) Interpolate (-6 dB)1  
Equal Rate Equal Rate  
Note:  
1. With 15-bit overflow protection. All other modes on both  
parts limit to 16 bits.  
Pin Assignments  
SO  
SO  
SO  
7
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
GND  
12  
11  
10  
SO  
SO  
SO  
1
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
GND  
8
V
12  
11  
10  
DD  
2
V
9
SI  
10  
SI  
9
SI  
8
SI  
7
SI  
6
SI  
5
SI  
4
SI  
3
DD  
3
SI  
10  
SI  
9
SI  
8
SI  
7
SI  
6
SI  
5
SI  
4
SI  
3
SO  
10  
11  
12  
13  
14  
15  
16  
17  
9
SO  
4
SO  
9
8
8
TMC2242A  
TMC2242B  
SO  
5
GND  
TMC2242A  
TMC2242B  
GND  
6
V
DD  
V
7
SO  
7
SO  
6
SO  
5
SO  
4
DD  
SO  
7
SO  
6
SO  
5
SO  
8
9
10  
11  
V
DD  
V
DD  
4
65-2242A-02  
65-2242A-02  
44 Lead PLCC  
44 Lead MQFP  
2