Figure 3 - Typical Interface Circuit (Single-Ended Operational Design)
1 µF
(TTL to PECL
Translator)
A+5V
300
+
50
1 GND(THA)
XUF (Dependent on Frequency)
Analog In
A+5V
0.01 µF
3
+
7
OP191
4
6
22
0.1 µF
50
2 GND(THA)
3 Analog IN
4 GND(SUB)
5 GND(THA)
6 GND(CAP)
CLK
CLK
AVCC(THA)
AVCC(THA)
AVCC(THA)
28
27
26
4.7 µF
25
24
23
22
21
20
19
18
17
16
15
0.01 µF
22
N/C
N/C
N/C
N/C
N/C
A+5V
0.01 µF
OUT
+
A+5V
10
50
1
2
3
4
MC100ELT22
0.01 µF
(+3.0 V)
(Optional Level-Shift Circuit)
Q0
Q0
Q1
Q1
VCC 8
7
DO
D1
GND
6
5
0.1 µF
TTL Clock
(Sample Clock, up to 100 MHz)
2 -
7 GND(THA)
(+2.5 V)
N/C
+
SPT9110
AVCC(THA)
AVCC(THA)
OUT+
INV A
INV B
OUT-
AVCC(INV)
AVCC(INV)
AVCC(ESD)
8 GND(THA)
9 REF IN
10 REF OUT
11 AVCC(Ref)
12 GND(Ref)
0.01 µF
13 GND(SUB)
14 GND(INV)
4.7 µF
0.01 µF
A+5V
4.7 µF
+
Notes:
1. Input signal is typically at a +2.5 V offset. The optional level-shift circuit may be eliminated if
driving from a source that already provides for this offset.
2. The device may be operated from -5 V supply on GND pins and 0 V on AVCC pins. All input and
output pins will be shifted by -5 V. The use of an ECL level may be used to drive the clock inputs.
3. VCC (ESD) is the high voltage for the ESD protection diodes and must be connected in all
applications. NOTE: It should be tied to VCC (THA), not to VCC (INV).
Figure 4 - Typical Interface Circuit (Differential Operational Design)
1 µF
(TTL to PECL
Translator)
A+5V
300
+
50
1 GND(THA)
XUF (Dependent on Frequency)
Analog In
A+5V
0.01 µF
3
+
7
OP191
4
6
22
0.1 µF
50
2 GND(THA)
3 Analog IN
4 GND(SUB)
5 GND(THA)
6 GND(CAP)
CLK
CLK
AVCC(THA)
AVCC(THA)
AVCC(THA)
28
27
26
4.7 µF
25
+
24
23
22
21
20
19
18
17
16
15
22
OUT-
0.01 µF
+
4.7 µF
A+5V
22
0.01 µF
OUT+
A+5V
10
50
1
2
3
4
MC100ELT22
0.01 µF
(+3.0 V)
(Optional Level-Shift Circuit)
Q0
Q0
Q1
Q1
VCC 8
7
DO
D1
GND
6
5
0.1 µF
TTL Clock
(Sample Clock, up to 100 MHz)
2 -
7 GND(THA)
(+2.5 V)
+
4.7 µF
0.01 µF
A+5V
4.7 µF
0.01 µF
+
11 AVCC(Ref)
12 GND(Ref)
13 GND(SUB)
14 GND(INV)
8 GND(THA)
9 REF IN
10 REF OUT
SPT9110
AVCC(THA)
AVCC(THA)
OUT+
INV A
INV B
OUT-
AVCC(INV)
AVCC(INV)
AVCC(ESD)
(Differential Output)
Notes:
1. Input signal is typically at a +2.5 V offset. The optional level-shift circuit may be eliminated if
driving from a source that already provides for this offset.
2. The device may be operated from -5 V supply on GND pins and 0 V on AVCC pins. All input and
output pins will be shifted by -5 V. The use of an ECL level may be used to drive the clock inputs.
3. VCC (ESD) is the high voltage for the ESD protection diodes and must be connected in all
applications. NOTE: It should be tied to VCC (THA), not to VCC (INV).
SPT9110
7
11/12/98
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
