SPT7851
DATA SHEET
Sampling
Points
N-1
N
N+1
t
AP
A
IN
CLK
N+2
N+6
N+7
N+8
t
D
D
OUT
N-2
N-1
N
Figure 1: Timing Diagram
General Description
The SPT7851 is an ultra-low power, 10-bit, 20 MSPS ADC.
It has a pipelined architecture and incorporates digital error
correction of all 10 bits. This error correction ensures good
linearity performance for input frequencies up to Nyquist.
The inputs are fully differential, making the device insensi-
tive to system-level noise. This device can also be used in a
single-ended mode. (See analog input section.) With the
power dissipation roughly proportional to the sampling rate,
this device is ideal for very low power applications in the
range of 1 to 20 MSPS.
Typical Interface Circuit
The SPT7851 requires few external components to achieve
the stated operation and performance. Figure 2 shows the
typical interface requirements when using the SPT7851
in normal circuit operation. The following sections provide
a description of the functions and outline critical perfor-
mance criteria to consider for achieving the optimal device
performance.
+3.3V
Ref- In
(+1.15 V)
4.7
µF
+
.01
µF
10
µF
+
CLK
IN
(3V Logic)
+3.3V
+3.3V Digital
Ref+ In
(+2.15 V)
+
4.7
µF
.01
µF
11
12
N/C
N/C
N/C
.01
µF
0.1
µF
1
GND
CLK
N/C
Decoupling
Cap
VDD2
VDD1
VDD3
VRef-
VRef+
VDD1
VDD1
VDD2
V
DD3
44
DNC
DNC
D0
(LSB)
90
µA
9.5
µA
.01
µF
(+1.65 V)
GND
Bias1
Bias2
VCM
GND
U1
SPT7851
D1
D2
D3
D4
D5
D6
D7
D9
Interfacing
3V Logic
RF
IN
51Ω
68 pF
VIN+
VIN-
22
Minicircuit
T1-6T
GND
GND
34
D8
(MSB)
23
33
AGND
Note: 1. All V
DD1
, V
DD2
and V
DD3
should be tied together.
2. FB = Ferrite Bead; must be placed as close to U1 as possible.
FB
DGND
Figure 2: Typical Interface Circuit
REV. 1B October 2003
5
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
