DATA SHEET
SPT7851
Electrical Specifications
(
T
A
= T
MIN
–T
MAX
, V
DD1
= V
DD2
= V
DD3
= 3.3V, V
REF–
= 1.0V, V
REF+
= 2.0V, Common Mode Voltage = 1.65V,
ƒ
CLK
= 20 MSPS,
Bias1 = 90
µ
A, Bias2 = 9.5
µ
A, Differential Input, Duty Cycle = 50%; unless otherwise noted)
Parameter
DC Accuracy
Resolution
Differential Linearity
Integral Linearity
No Missing Codes
Analog Input
Input Voltage Range (differential)
Common Mode Input Voltage
Input Capacitance
Input Bandwidth (large signal)
Offset (mid-scale)
Gain Error
Reference Voltages
Reference Input Voltage Range
Negative Reference Voltage (V
REF–
)
Positive Reference Voltage (V
REF+
)
Common Mode Output Voltage (V
CM
)
V
REF+
Current
V
REF–
Current
Switching Performance
Maximum Conversion Rate
Pipeline Delay (see Figure 1)
Aperture Delay Time (T
AP
)
Aperture Jitter Time
Dynamic Performance
Signal-To-Noise Ratio
Effective Number of Bits
Total Harmonic Distortion
Signal-To-Noise and Distortion
Spurious Free Dynamic Range
Differential Phase
Differential Gain
ƒ
IN
= 5MHz
ƒ
IN
= 10MHz
ƒ
IN
= 5MHz
ƒ
IN
= 10MHz
ƒ
IN
= 5MHz
ƒ
IN
= 10MHz
ƒ
IN
= 5MHz
ƒ
IN
= 10MHz
ƒ
IN
= 5MHz
ƒ
IN
= 10MHz
VI
V
VI
V
VI
V
VI
V
VI
V
V
V
62
56
9.0
57
58
58
9.3
9.0
-68
-60
58
56
70
61
0.2
0.5
-61
dB
dB
Bits
Bits
dB
dB
dB
dB
dB
dB
deg
%
VI
IV
V
V
20
7.5
5
10
MHz
CLK
ns
ps-rms
I
O
= -1
µ
A
V
REF+
– V
REF–
IV
IV
IV
VI
V
V
0.6
0.9
1.9
1.3
1.0
1.0
2.0
1.65
35
-25
1.7
1.3
2.9
1.8
V
V
V
V
µ
A
µ
A
V
IN+
= V
IN-
= V
CM
IV
IV
V
V
V
V
±0.6
1.2
±1.0
1.65
1.4
120
±1.0
0.3
±1.7
1.9
V
V
pF
MHz
%FSR
%FSR
V
V
VI
10
±0.6
±0.75
Guaranteed
Bits
LSB
LSB
Conditions
Test Level
Min
Typ
Max Units
2
REV. 1B October 2003
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
