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SPT7721SIT 参数 Datasheet PDF下载

SPT7721SIT图片预览
型号: SPT7721SIT
PDF下载: 下载PDF文件 查看货源
内容描述: 8 - BIT , 250 MSPS ADC,具有解复产出 [8-BIT, 250 MSPS ADC WITH DEMUXED OUTPUTS]
分类和应用: 输出元件
文件页数/大小: 11 页 / 192 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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POWER DOWN MODE
To save on power, the SPT7721 incorporates a power-
down function. This function is controlled by the signal on
pin PD. When pin PD is set high, the SPT7721 enters the
power-down mode. All outputs are set to high impedance.
In the power-down mode the SPT7721 dissipates 10 mW
typically.
REFERENCES
To save on parts count, design time, and PC board real
estate, the SPT7721 utilizes an internal reference. No
other external components are required to implement this
feature.
COMMON MODE VOLTAGE REFERENCE CIRCUIT
The SPT7721 has an on-board common-mode voltage
reference circuit (V
CM
). It is 2.5 volts and is capable of driv-
ing 50 µA loads typically. The circuit is commonly used to
drive the center tap of the RF transformer in fully differen-
tial applications. For single-ended applications, this output
can be used to provide the level shifting required for the
single-to-differential converter conversion circuit.
CLOCK INPUT
The clock input on the SPT7721 can be driven by either a
single-ended or double-ended clock circuit and can handle
TTL, PECL, and CMOS signals. When operating at high
sample rates it is important to keep the pulse width of the
clock signal as close to 50% as possible. For TTL/CMOS
single-ended clock inputs, the rise time of the signal also
becomes an important consideration.
DIGITAL OUTPUTS
The output circuitry of the SPT7721 has been designed to
be able to support three separate output modes. The
demuxed (double-wide) mode supports either parallel
aligned or interleaved data output. The single-channel
mode is not demuxed and can support direct output at
speeds up to 125 MSPS. The output format is straight
binary (table I).
Table I – Output Data Format
Output Code
D7–D0
+FS
1111 1111
+FS – 1/2 LSB
1111 111Ø
+1/2 FS
ØØØØ ØØØØ
–FS + 1/2 LSB
0000 000Ø
–FS
0000 0000
Ø indicates the flickering bit between logic 0 and 1
Analog Input
The data output mode is set using the DMODE
1
and
DMODE
2
inputs (pins 32 & 31 respectively). Table II
describes the mode switching options.
Table II – Output Data Modes
Output Mode
DMODE
1
Parallel Dual Channel Output
0
Interleaved Dual Channel Output
0
Single Channel Data Output
(Bank A only 125 MSPS max)
1
DMODE
2
0
1
X
EVALUATION BOARD
The EB7721/22 evaluation board is available to aid design-
ers in demonstrating the full performance of the SPT7721.
This board includes a clock driver and reset circuit, adjust-
able references and common mode, a single-ended to dif-
ferential input buffer and a single-ended to differential
transformer (1:1). An application note (AN7721/22) de-
scribing the operation of this board, as well as information
on the testing of the SPT7721, is also available. Contact
the factory for price and availability of the EB7721/22.
SPT7721
9
11/8/01