Figure 2 – Dual Mode Timing Diagram
N-2
2.5 CLK Cycles
tap
N-1
N
N+1
of Latency
N+2
N+3
N+4
Vin
/CLK
CLK
Refer to AN7722
U6-Reset
/Reset
Reset
550ps
550ps
t
reset
ts
tpd1
tpd1
tpd1
INTERLEAVED DATA OUTPUT
Port A
Port B
N-5
N-6
N-4
Invalid Data
N-1
N-2
N
N+1
tpd2
Port A
Port B
DCLKOUT
/DCLKOUT
tpd3
N-7
N-6
N-5
N-4
PARALLEL DATA OUTPUT
Invalid Data
N-2
N
N-1
tpd2
N-2
2.5 CLK
Cycles o
f Latenc
y
tap
N-1
N
N+1
N+2
N+3
N+4
Vin
/CLK
CLK
Refer to AN7722
U6-Reset
/Reset
Reset
550ps
550ps
t
reset
ts
tpd1
tpd1
tpd1
INTERLEAVED DATA OUTPUT
Port A
Port B
N-6
N-5
N-4
Invalid Data
N-2
N-1
N
N+1
tpd2
Port A
Port B
/DCLKOUT
DCLKOUT
PARALLEL DATA OUTPUT
N-6
N-5
tpd1
Invalid Data
N-2
N
N-1
Data Output Possibilities w/o Reset
SPT7721
7
11/8/01