READING THE OUTPUT DATA
The output data buffers remain in a high impedance state until
the following four conditions are met: R/
C
is high, STS is low,
CE is high, and
CS
is low. The data lines become active in
response to the four conditions and output data according to
the conditions of 12/
8
and Ao. The timing diagram for this
process is shown in figure 2. When 12/
8
is high, all 12 data
outputs become active simultaneously and the Ao input is
ignored. This is for easy interface to a 12 or 16-bit data bus.
The 12/
8
input is usually tied high or low, although it is
TTL/CMOS compatible. When 12/
8
is low, the output is
separated into two 8-bit bytes as shown below.
Figure 8 - Output When 12/
8
Is Low
SAMPLE-AND-HOLD (S/H) CONTROL MODE
This control mode is provided to allow full use of the internal
S/H, eliminating the need for an external S/H in most applica-
tions. The SPT574 in the control mode also eliminates the
need for one of the control signals, usually the convert
command. The command that puts the internal S/H in the
hold state also initiates a conversion, reducing time con-
straints in many systems. As soon as the conversion is
completed the internal S/H immediately begins slewing to
track the input signal. See figure 9.
In the control mode it is assumed that during the required 4
µs
acquisition time the signal is not slewing faster than the
slew rate of the SPT574. No assumption is made about the
input level after the convert command arrives since the input
signal is sampled and conversion begins immediately after
the convert command. This means that the convert com-
mand can be used to switch an input multiplexer or change
gains on a programmable gain amplifier, allowing the input
signal to settle before the next acquisition at the end of the
conversion. Because aperture jitter is minimized by the
internal S/H, a high input frequency can be converted without
an external S/H. See table II.
Table II - Conversion Timing (V
EE
= +5 V)
S/H Control Mode
Min
Typ Max
22
16
18
12
4
20
0.3
25
18
BYTE 1
X X X X
MSB
X X X X
BYTE 2
X X X X
LSB
O O O O
This configuration makes it easy to connect to an 8-bit data
bus as shown in figure 7. The Ao control can be connected to
the least significant bit of the address bus in order to store the
output data into two consecutive memory locations. When Ao
is pulled low, the 8 MSBs are enabled only. When Ao is high,
the 4 MSBs are disabled, bits 4 through 7 are forced to a zero
and the four LSBs are enabled. The two byte format is left
justified data as shown above and can be considered to have
a decimal point or binary to the left of byte 1.
Ao may be toggled without damage to the converter at any
time. Break-before-make action is guaranteed between the
two data bytes. This assures that the outputs in figure 7 will
never be enabled at the same time.
In figure 2, it can be seen that a read operation usually begins
after the conversion is completed and STS is low. If earlier
access is needed, the read can begin no later than the
addition of time t
DD
and t
HS
before STS goes low.
Figure 9 - S/H Control Mode Timing (V
EE
= +5 V)
Parameter
Throughput Time (t
AQ
+
tC
)
12-Bit Conversions
8-Bit Conversions
Conversion Time (t
C
)
12-Bit Conversions
8-Bit Conversions
Acquisition Time(t
AC
)
Aperture Delay (t
AP
)
Aperture Uncertainty (t
J
)
Units
µs
µs
µs
µs
µs
ns
ns
R/C
t
AP
Signal Acquisition
t
C
Conversion
Signal Acquisition
t
AQ
SPT574
9
8/1/00
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
