ELECTRICAL SPECIFICATIONS
T
A
= T
MIN
to T
MAX
, V
EE
= 0 to +5 V, V
DD
= +5 V, f
S
= 40 kHz, f
IN
= 10 kHz, unless otherwise specified.
PARAMETER
TEST
CONDITIONS
TEST
LEVEL
SPT574C
MIN
TYP
MAX
SPT574B
MIN
TYP
MAX
UNITS
AC ELECTRICAL CHARACTERISTICS
4
Convert Mode Timing
t
DSC
STS Delay from CE
t
HEC
CE Pulse Width
t
SSC
CS to CE Setup
t
HSC
CS Low during CE High
t
SRC
R/C to CE Setup
t
HRC
R/C Low During CE High
t
SAC
Ao to CE Setup
t
HAC
Ao Valid During CE High
t
C
Conversion Time
5
12-Bit Cycle
8-Bit Cycle
Read Mode Timing
t
DD
Access Time from CE
t
HD
Data Valid After CE Low
t
HL
Output Float Delay
t
SSR
CS to CE Setup
t
SRR
R/C to CE Setup
t
SAR
Ao to CE Setup
t
HSR
CS Valid After CE Low
t
HRR
R/C High After CE Low
t
HS
STS Delay After Data Valid
t
HAR
Ao Valid after CE Low
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
VI
60
30
20
20
0
20
20
22
16
75
35
100
0
25
25
18
150
25
150
50
0
50
0
1000
0
300
50
200
50
50
50
50
50
0
50
60
30
20
20
0
20
20
22
16
75
35
100
0
25
25
18
150
150
200
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
1000
ns
ns
ns
50
50
50
50
50
0
50
25
50
0
50
0
0
300
50
400
400
Note 4: Time is measured from 50% level of digital transitions.
Note 5: Includes acquisition time.
Figure 1 - Convert Mode Timing Diagram
Figure 2 - Read Mode Timing Diagram
CE
CE
CS
t
SSC
t
HEC
CS
t
SSR
t
HSR
t
HRR
t
SRC
R/C
t
HSC
R/C
t
SRR
t
HRC
Ao
Ao
t
SAC
STS
t
SAR
t
HAR
t
HAC
STS
t
DSC
t
C
t
HS
HIGH
DB11-DB0
IMPEDANCE
DATA
VALID
t
HD
DB11-DB0
High Impedance
t
DD
t
HL
SPT574
4
8/1/00
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
