POWER SUPPLY SEQUENCING
The required power-up sequence is as follows: V
SS
(or
V
DD
) first, V
DD
(or V
SS
) second, and then REF_. The
sequence in which V
DD
and V
SS
come up is not critical.
However, REF_ must come up after V
DD
and V
SS
are
established.
CADEKA strongly recommends that the digital input pins
be driven only after V
DD
and V
SS
are established. Driving
a digital input prior to establishing supplies will violate a
condition outlined in the Input Voltages section (see the
Absolute Maximum Ratings on page 2 of this data sheet)
and cause damage to the part. If either REF_ or the digi-
tal inputs must come up before V
DD
and V
SS
, due to sys-
tem constraints, limit the current to the REF_ or digital
input pins to less than 1 mA.
This recommended power-up sequence must be
executed in reversed order for power-down. It should be
noted that none of the Absolute Maximum Rating condi-
tions are violated during power-up and power-down.
Replacing VDAC in the equation gives the output
voltage.
V
OUT
xx=2
2
13
(
REFxx
)
−
REFxx
=
REFxx
2
12
−
1
=
REFxx
4096
−
1
D
D
D
1 LSB = REFxx
1
4096
D ranges from 0 to 8191 (2
13
–1).
Table IV – Input Code/Output Tables
Bipolar (AGNDxx = 0 V)
Input
1 1111 1111 1111
1 0000 0000 0001
1 0000 0000 0000
0 1111 1111 1111
0 0000 0000 0001
0 0000 0000 0000
Output
+REFxx (4095/4096)
+REFxx (1/4096)
0V
–REFxx (1/4096)
–REFxx (4095/4096)
–REFxx
ANALOG OUTPUTS
The voltage outputs to the SPT5400 are buffered inter-
nally by precision amplifiers with a 2.4 V/µs typical slew
rate. The typical settling time to
±1/2
LSB, with a full-
scale transition at the outputs, is 7
µs.
Each DAC output
is protected against a short to GND or AGNDxx. The typi-
cal short-circuit currents are 25 mA when the DAC is
at positive full scale, and 2.5 mA when the DAC is at
negative full scale.
BIPOLAR OUTPUT VOLTAGE RANGE
(AGNDxx = 0 V)
For symmetrical bipolar operation, AGNDxx should be
tied to the system ground. The relationship between the
output voltage and the digital code is shown in table IV.
The output voltage of the DAC ladder (VDAC) is multi-
plied by 2 and level-shifted by the reference voltage. The
output voltage of the amplifier is given by the following
equation:
V
OUT
= 2(VDAC) – REFxx
Where VDAC is the voltage at the noninverting input of
the amplifier and REFxx is the voltage at the reference
input of the DAC.
With AGNDxx connected to the system ground, the out-
put voltage of the DAC ladder is:
VDAC = (D/2
13)
REFxx
Where D is the numeric value of the DAC’s binary input
code.
Positive Unipolar (AGNDxx = REFxx/2)
Input
Output
1 1111 1111 1111
+REFxx (8191/8192)
1 0000 0000 0000
+REFxx/2
0 0000 0000 0000
0V
POSITIVE UNIPOLAR OUTPUT VOLTAGE RANGE
(AGNDxx = REFxx/2)
For positive unipolar operation, AGNDxx should be set to
REFxx/2. The relationship between the output voltage
and the digital code is shown in table IV. For example, if a
4.096 V reference is used, AGNDxx should be offset by
2.048 V. This results in a unipolar output voltage of 0 to
4.0955 V, where 1 LSB = 500
µV.
the maximum current
out of any AGNDxx pin is:
I
AGNDXX
=
REFxx
−
AGNDxx
5 k
Ω
CUSTOM OUTPUT VOLTAGE RANGE
If the voltage at the REFxx input is higher than the volt-
age at the AGNDxx input, the AGNDxx inputs can be off-
set by any voltage within the supply rails. One way to
achieve this is to add positive offset to AGNDxx by select-
ing the reference voltage and the voltage at AGNDxx
such that the resulting output voltages do not come within
±0.5
V of the supply rails. Another way is to digitally offset
AGNDxx by connecting one DAC output to one or more
AGNDxx inputs. Note that a DAC output should not be
connected to its own AGNDxx input.
SPT5400
5
5/15/00
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
