TEST LEVEL CODES
All electrical characteristics are subject
to the following conditions:
All parameters having min/max specifi-
cations are guaranteed. The Test Level
column indicates the specific device
testing actually performed during pro-
duction and Quality Assurance inspec-
tion. Any blank section in the data
column indicates that the specification
is not tested at the specified condition.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at T
A
= +25
°C,
and sample tested at the
specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characteriza-
tion data.
Parameter is a typical value for information purposes only.
100% production tested at T
A
= +25
°C.
Parameter is guaranteed over
specified temperature range.
Figure 1 – Timing Diagram
CS
t
5
t
2
t
9
t
10
t
1
t
6
WR
A0–A2
t
7
t
8
NOTES:
1. All input rise and fall times
are measured from 10% to
90% of +5 V. t
R
= t
F
= 5 ns.
2. If
LD
is activated while
WR
is
low,
LD
must stay low for t
3
or
longer after
WR
goes high.
D0–D12
t
4
t
3
LD
Table I – Timing Parameters
PARAMETER
SYMBOL MIN TYP MAX
CS
Pulse Width Low
t
1
50
WR
Pulse Width Low
t
2
50
LD
Pulse Width Low
t
3
50
CLR
Pulse Width Low
t
4
100
CS
to
WR
Low
t
5
0
CS
High to
WR
High
t
6
0
Data Valid to
WR
Setup
t
7
20
Data Valid to
WR
Hold
t
8
0
Address Valid to
WR
Setup t
9
10
Address Valid to
WR
Hold
t
10
0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPT5400
3
5/15/00
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
