Data Sheet
Symbol
Clock Inputs
Maximum Conversion Rate
Minimum Conversion Rate
65
20
MSPS
MSPS
Parameter
Sleep Channel Mode Savings
Conditions
Power dissipation savings per channel off
Min
Typ
38
Max
Units
mW
CDK8307
12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS
Electrical Characteristics - CDK8307E
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 12-bit output, unless otherwise noted)
Symbol
Performance
SNR
SINAD
SFDR
HD2
HD3
ENOB
Crosstalk
Parameter
Conditions
F
IN
= 8MHz
F
IN
= 30MHz
F
IN
= 8MHz
F
IN
= 30MHz
F
IN
= 8MHz
F
IN
= 30MHz
F
IN
= 8MHz
F
IN
= 30MHz
F
IN
= 8MHz
F
IN
= 30MHz
F
IN
= 8MHz
F
IN
= 30MHz
See note (1) on page 13
Min
68.5
68
74
85
75
Typ
70.1
70
69.6
69.5
77
76
90
90
77
76
11.3
11.3
95
173
Max
Units
dBFS
dBFS
dBFS
dBFS
dBc
dBc
dBc
dBc
dBc
dBc
bits
bits
dBc
mA
mA
mW
mW
mW
µW
mW
mW
mW
MSPS
Signal to Noise Ratio
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
Effective number of Bits
Power Supply
Analog supply current
Digital supply current
Analog power Dissipation
Digital power Dissipation
Total power Dissipation
Power Down Dissipation
Sleep Mode Dissipation
Sleep Channel Mode Dissipation
Sleep Channel Mode Savings
Power down mode
Deep sleep mode
All channels. in sleep ch. mode (light sleep)
Power dissipation savings per channel off
80
40
Digital and output driver supply
88
312
158
470
10
56
116
44
Clock Inputs
Maximum Conversion Rate
Minimum Conversion Rate
MSPS
Digital and Timing Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, unless otherwise noted)
Symbol
Clock Inputs
Duty Cycle
Compliance
Input range, differential
Input range, sine
Input range, CMOS
Input common mode voltage
Input capacitance
Differential input swing
Differential input swing, sine wave clock input
CLKN connected to ground
Keep voltages within gnd and voltage of OVDD
Differential
0.3
2
20
±200
±800
V
OVDD
V
OVDD
-0.3
80
%high
mV
pp
mV
pp
mV
pp
V
pF
CMOS, LVDS, LVPECL
Parameter
Conditions
Min
Typ
Max
Units
Rev 1A
©2009 CADEKA Microcircuits LLC
www.cadeka.com
13
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
