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CDK8307BILP64 参数 Datasheet PDF下载

CDK8307BILP64图片预览
型号: CDK8307BILP64
PDF下载: 下载PDF文件 查看货源
内容描述: 12月13日位,四十零分之二十零/ 50/ 65 / 80MSPS ,八通道,超低功耗ADC LVDS [12/13-bit, 20/40/50/65/80MSPS, Eight Channel, Ultra Low Power ADC with LVDS]
分类和应用:
文件页数/大小: 31 页 / 1408 K
品牌: CADEKA [ CADEKA MICROCIRCUITS LLC. ]
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Data Sheet  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
FIN = 8MHz  
75  
82  
77  
dBc  
dBc  
dBc  
dBc  
dBc  
dBc  
bits  
bits  
dBc  
SFDR  
Spurious Free Dynamic Range  
FIN = 30MHz  
FIN = 8MHz  
85  
75  
95  
HD2  
Second order Harmonic Distortion  
Third order Harmonic Distortion  
Effective number of Bits  
FIN = 30MHz  
FIN = 8MHz  
95  
82  
HD3  
FIN = 30MHz  
FIN = 8MHz  
77  
11.6  
11.5  
95  
ENOB  
FIN = 30MHz  
See note (1) on page 13  
Crosstalk  
Power Supply  
111  
73  
mA  
mA  
Analog supply current  
Digital and output driver supply  
Digital supply current  
200  
132  
331  
10  
mW  
mW  
mW  
µW  
Analog power Dissipation  
Digital power Dissipation  
Total power Dissipation  
Power Down Dissipation  
Sleep Mode Dissipation  
Sleep Channel Mode Dissipation  
Sleep Channel Mode Savings  
Power down mode  
Deep sleep mode  
46  
mW  
mW  
mW  
All channels. in sleep ch. mode (light sleep)  
Power dissipation savings per channel off  
83  
31  
Clock Inputs  
50  
MSPS  
MSPS  
Maximum Conversion Rate  
Minimum Conversion Rate  
20  
Electrical Characteristics - CDK8307D  
(AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 14-bit output, unless otherwise noted)  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
Performance  
FIN = 8MHz  
70  
69  
75  
85  
75  
72.2  
71.5  
71.5  
70.7  
82  
dBFS  
dBFS  
dBFS  
dBFS  
dBc  
SNR  
Signal to Noise Ratio  
FIN = 30MHz  
FIN = 8MHz  
SINAD  
SFDR  
HD2  
Signal to Noise and Distortion Ratio  
Spurious Free Dynamic Range  
Second order Harmonic Distortion  
Third order Harmonic Distortion  
Effective number of Bits  
FIN = 30MHz  
FIN = 8MHz  
FIN = 30MHz  
FIN = 8MHz  
77  
dBc  
95  
dBc  
FIN = 30MHz  
FIN = 8MHz  
95  
dBc  
82  
dBc  
HD3  
FIN = 30MHz  
FIN = 8MHz  
77  
dBc  
11.6  
11.5  
95  
bits  
ENOB  
FIN = 30MHz  
See note (1) on page 13  
bits  
Crosstalk  
dBc  
Power Supply  
143  
83  
mA  
mA  
Analog supply current  
Digital and output driver supply  
Digital supply current  
257  
149  
405  
10  
mW  
mW  
mW  
µW  
Analog power Dissipation  
Digital power Dissipation  
Total power Dissipation  
Power Down Dissipation  
Sleep Mode Dissipation  
Sleep Channel Mode Dissipation  
Power down mode  
Deep sleep mode  
54  
mW  
mW  
All channels. in sleep ch. mode (light sleep)  
103  
©2009 CADEKA Microcircuits LLC  
www.cadeka.com  
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