PRELIMINARY Data Sheet
Electrical Characteristics - CDK2308B
(AV =1.8V, DV =1.8V, DV
=1.8V, OV =2.5V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal,
DD
DD
DDCLK
DD
13-bit output, unless otherwise noted)
symbꢀl
Parameꢁer
cꢀndiꢁiꢀnꢂ
Min
typ
Max
uniꢁꢂ
Performance
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 30MHz
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 30MHz
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 30MHz
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 30MHz
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 30MHz
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 30MHz
61.6
61.6
61.6
61.5
61.6
61.6
61.2
61.4
78.8
82.3
72.0
82.5
-87.9
-92.0
-84.8
-88.8
-81.8
-85.7
-72.0
-83.9
9.9
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
SNR
Signal to Noise Ratio
SNDR
SFDR
HD2
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
HD3
dBc
dBc
bits
9.9
bits
ENOB
XTALK
Effective number of Bits
Crosstalk
9.9
bits
9.9
bits
Signal crosstalk between channels, FIN1
8MHz, FIN0 = 9.9MHz
=
-102
dBc
Power Supply
AIDD
Analog Supply Current
Digital Supply Current
14.4
3.4
mA
mA
mA
DIDD
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1MHz
5.1
OIDD
Output Driver Supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
4.2
mA
Analog Power Dissipation
Digital Power Dissipation
25.9
16.6
mW
mW
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
42.5
mW
Total Power Dissipation
Power Down Dissipation
Sleep Mode 1
9.7
µW
mW
mW
Power Dissipation, Sleep mode one channel
Power Dissipation, Sleep mode both channels
25.7
11.3
Sleep Mode 2
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
40
MSPS
MSPS
20
©2008 CADEKA Microcircuits LLC
www.cadeka.com
7
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
