PRELIMINARY Data Sheet
Digital and Timing Electrical Characteristics
(AV =1.8V, DV =1.8V, DV
=1.8V, OV =2.5V, 50 MSPS clock, 50% clock duty cycle, -1 dBFS input signal,
DD
DD
DDCLK
DD
5pF capacitive load, unless otherwise noted)
symbꢀl
Parameꢁer
cꢀndiꢁiꢀnꢂ
Min
typ
Max
uniꢁꢂ
Clock Inputs
Duty Cycle
Compliance
20
80
% high
CMOS, LVDS, LVPECL, Sine Wave
-200
-800
0.3
200
800
mVpp
mVpp
V
Differential input swing
Input Range
Differential input swing, sine wave clock input
Keep voltages within ground and voltage of OVDD
Differential
Input Common Mode Voltage
Input Resistance
VOVDD -0.3
TBD
1.7
kΩ
Input Capacitance
pF
Differential
Timing
TPD
From Power Down Mode to References has
eached 99% of final value
Start Up Time Active Mode
580
clk cycles
TSLP
TOVR
TAP
Start Up Time Mode
Out Of Range Recovery Time
Aperture Delay
From Sleep Mode to Active
0.5
4
µs
clk cycles
ns
0.8
12
4
TLAT
Pipeline Delay
clk cycles
ns
5pF load on output bits
10pF load on output bits
Relative to CLK_EXT
TD
Output Delay (see timing diagram)
Output Delay (see timing diagram)
TBD
ns
TDC
2
ns
Logic Inputs
VOVDD ≥ 3.0V
2
V
V
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
VOVDD = 1.7V – 3.0V
VOVDD ≥ 3.0V
0.8 • VOVDD
0
0.8
0.2 • VOVDD
10
V
VOVDD = 1.7V – 3.0V
0
V
IIH
High Level Input Leakage Current
Low Level Input Leakage Current
Input Capacitance
-10
-10
µA
µA
pF
IIL
10
CI
3
Logic Outputs
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
-0.1 +VOVDD
V
V
0.1
5
Post-driver supply voltage equal to pre-driver
supply voltage VOVDD = VOCVDD
Post-driver supply voltage above 2.25V (1)
pF
CL
Max Capacitive Load
10
pF
Nꢀꢁe:
(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents
and resulting switching noise at a minimum.
©2008 CADEKA Microcircuits LLC
www.cadeka.com
10
CADEKA [ CADEKA MICROCIRCUITS LLC. ]
