Data Sheet
Electrical Characteristics - CDK2307D
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
70.4
72
71.7
71.2
70.7
70.5
70.5
70.4
70.3
77
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
SNR
Signal to Noise Ratio
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
69.5
74
SINAD
SFDR
HD2
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
78
dBc
78
dBc
78
dBc
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
-80
-74
11.3
-95
dBc
-90
dBc
-90
dBc
-85
dBc
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
-77
dBc
-78
dBc
HD3
-78
dBc
-78
dBc
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
11.4
11.4
11.4
11.4
bits
bits
ENOB
XTALK
Effective number of Bits
Crosstalk
bits
bits
Signal crosstalk between channels, FIN1
8MHz, FIN0 = 9.9MHz
=
-95.0
dB
Power Supply
AIDD
Analog Supply Current
Digital Supply Current
39.7
6.0
mA
mA
mA
DIDD
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1MHz
9.4
OIDD
Output Driver Supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
7.7
mA
Analog Power Dissipation
Digital Power Dissipation
71.5
30
mW
mW
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
101.5
mW
Total Power Dissipation
Power Down Dissipation
Sleep Mode 1
9.1
µW
mW
mW
Power Dissipation, Sleep mode one channel
Power Dissipation, Sleep mode both channels
66.4
24.1
Sleep Mode 2
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
80
MSPS
MSPS
65
©2009 CADEKA Microcircuits LLC
www.cadeka.com
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