Data Sheet
Electrical Characteristics - CDK2307C
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 65MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
71.6
72.6
71.8
71.5
70.4
71.7
71.7
71.7
70
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
SNR
Signal to Noise Ratio
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
70.5
75
SINAD
SFDR
HD2
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
81
84
dBc
79
dBc
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
77
dBc
-85
-75
11.4
-95
-95
-95
-95
-81
-84
-79
-79
11.6
11.6
11.5
11.3
dBc
dBc
dBc
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
dBc
dBc
dBc
HD3
dBc
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
dBc
bits
bits
ENOB
XTALK
Effective number of Bits
Crosstalk
bits
FIN = 40MHz
bits
Signal crosstalk between channels, FIN1
8MHz, FIN0 = 9.9MHz
=
-95
dB
Power Supply
AIDD
Analog Supply Current
Digital Supply Current
32.8
5.0
mA
mA
mA
DIDD
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1MHz
8.2
OIDD
Output Driver Supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
6.6
mA
Analog Power Dissipation
Digital Power Dissipation
59.0
25.5
mW
mW
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
84.5
mW
Total Power Dissipation
Power Down Dissipation
Sleep Mode 1
9.3
µW
mW
mW
Power Dissipation, Sleep mode one channel
Power Dissipation, Sleep mode both channels
55.3
20.4
Sleep Mode 2
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
65
MSPS
MSPS
40
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www.cadeka.com
8
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