Data Sheet
Pin Configuration
QFN-64, TQFP-64
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3
4
5
6
CDK2307
7
CLK_EXT
QFN-64, TQFP-64
8
9
10
11
12
DVSSCLK
13
14
15
16
DVDDCLK
CLKP
CLKN
Pin Assignments
Pin No.
1, 18, 23
2
Pin Name
Description
DVDD
CM_EXT
AVDD
Digital and I/O-ring pre driver supply voltage, 1.8V
Common Mode voltage output
3, 9, 12
4, 5, 8
6, 7
Analog supply voltage, 1.8V
AVSS
Analog ground
IP0, IN0
IP1, IN1
DVSSCLK
DVDDCLK
CLKP
Analog input Channel 0 (non-inverting, inverting)
Analog input Channel 1 (non-inverting, inverting)
Clock circuitry ground
10, 11
13
14
Clock circuitry supply voltage, 1.8V
15
Clock input, non-inverting (Format: LVDS, PECL, CMOS/TTL, Sine Wave)
Clock input, inverting. For CMOS input on CLKP, connect CLKN to ground
Digital circuitry ground
16
CLKN
17, 64
19
DVSS
CLK_EXT_EN CLK_EXT signal enabled when low (zero). Tristate when high.
20
DFRMT
PD_N
Data format selection. 0: Offset Binary, 1: Two's Complement
21
Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up,
always apply Power Down mode before using Active Mode to reset chip.
22
OE_N_1
OVDD
OVSS
D1_0
Output Enable Channel 0. Tristate when high.
I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V.
Ground for I/O ring
24, 41, 58
25, 40, 57
26
27
28
29
Output Data Channel 1 (LSB, 13-bit output or 1Vpp full scale range )
Output Data Channel 1 (LSB, 12-bit output 2Vpp full scale range)
Output Data Channel 1
D1_1
D1_2
D1_3
Output Data Channel 1
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