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BL35P02 参数 Datasheet PDF下载

BL35P02图片预览
型号: BL35P02
PDF下载: 下载PDF文件 查看货源
内容描述: BL35P02是一款单芯片8位微控制器 [BL35P02 is a single-chip 8-bit micro-controller]
分类和应用: 微控制器
文件页数/大小: 27 页 / 308 K
品牌: BELLING [ BELLING ]
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上海贝岭股份有限公司  
Shanghai Belling Co., Ltd.  
BL35P02 DATASHEET  
In the indexed, 8-bit offset addressing mode, the effective address is obtained by adding the contents  
of the byte following the opcode to the contents of the index register. This mode of addressing is useful  
for selecting the kth element in an n element table. To use this mode, the table must begin in the  
lowest 256 memory locations and may extend through the first 511 memory locations (IFE is the last  
location which the instruction may access). Indexed 8-bit offset addressing can be used for ROM,  
RAM, or I/O. This is a 2-byte instruction with the offset contained in the byte following the opcode. The  
content of the index register (X) is not changed. The offset byte supplied in the instruction is an  
unsigned 8-bit integer.  
7.1.7 Indexed, 16-bit Offset Addressing Mode  
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the  
8-bit index register and the two bytes following the opcode. The content of the index register is not  
changed. These instructions are three bytes, one for the opcode and two for a 16-bit offset.  
7.1.8 Relative Addressing Mode  
The relative addressing mode is used only for branch instructions. Branch instructions, other than the  
branching versions of bit-manipulation instructions, generate two machine-code bytes: one for the  
opcode and one for the relative offset. Because it is desirable to branch in either direction, the offset  
byte is a signed twos-complement offset with a range of –127 to +128 bytes (with respect to the  
address of the instruction immediately following the branch instruction). If the branch condition is true,  
the contents of the 8-bit signed byte following the opcode (offset) are added to the contents of the  
program counter to form the effective branch address; otherwise, control proceeds to the instruction  
immediately following the branch instruction.  
7.2 Instruction Type  
There are 65 instructions in CPU, and can be divided into 5 types.  
1) Register/Memory Instructions  
2) Read/Modify-Write Instructions  
3) Branch Instructions  
4) Control Instructions  
5) bit manipulate Instructions  
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