PIN CONFIGURATION
Top View
VFBGA
Top View
TSSOP
DCLK
CS
DIN BUSY DOUT
+VCC
X+
1
2
3
4
5
6
7
8
16 DCLK
15 CS
1
2
3
4
5
6
7
A
B
C
D
E
F
NC
NC
Y+
14 DIN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
X–
13 BUSY
12 DOUT
11 PENIRQ
10 IOVDD
+VCC
+VCC
X+
PENIRQ
IOVDD
VREF
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Y–
GND
VBAT
AUX
NC
NC
NC
9
VREF
Y+
AUX
NC
NC
NC
NC
G
X–
Y–
GND GND VBAT
Top View
TSSOP
BUSY
DIN
1
2
3
4
12 AUX
11 VBAT
10 GND
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CS
DCLK
9
Y–
PIN DESCRIPTION
TSSOP PIN #
VFBGA PIN #
QFN PIN #
NAME
DESCRIPTION
1
2
B1 and C1
5
6
+VCC
X+
Power Supply
X+ Position Input
Y+ Position Input
X– Position Input
Y– Position Input
Ground
D1
3
E1
7
Y+
4
G2
8
X–
5
G3
9
Y–
6
G4 and G5
10
11
12
13
14
15
16
GND
VBAT
AUX
VREF
IOVDD
PENIRQ
DOUT
7
G6
E7
D7
C7
B7
A6
Battery Monitor Input
Auxiliary Input to ADC
8
9
Voltage Reference Input/Output
Digital I/O Power Supply
Pen Interrupt
10
11
12
Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high
impedance when CS is high.
13
14
15
A5
A4
A3
1
2
3
BUSY
DIN
Busy Output. This output is high impedance when CS is high.
Serial Data Input. If CS is low, data is latched on rising edge of DCLK.
Chip Select Input. Controls conversion timing and enables the serial input/output register.
CS high = power-down mode (ADC only).
CS
16
A2
4
DCLK
External Clock Input. This clock runs the SAR conversion process and synchronizes serial data
I/O.
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4
SBAS265C
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