ANALOG INPUT
When the converter enters the hold mode, the voltage
difference between the +IN and –IN inputs (as shown in
Figure 2) is captured on the internal capacitor array. The
input current into the analog inputs depends on the conver-
sion rate of the device. During the sample period, the source
must charge the internal sampling capacitor (typically 25pF).
After the capacitor has been fully charged, there is no further
input current. The rate of charge transfer from the analog
source to the converter is a function of conversion rate.
Figure 2 shows a block diagram of the input multiplexer on
the TSC2046, the differential input of the ADC, and the
differential reference of the converter. Table I and Table II
show the relationship between the A2, A1, A0, and SER/DFR
control bits and the configuration of the TSC2046. The
control bits are provided serially via the DIN pin—see the
Digital Interface section of this data sheet for more details.
+VCC
VREF
PENIRQ IOVDD
TEMP1
TEMP0
Level
Shifter
50kΩ
or
Logic
90kΩ
A2-A0
SER/DFR
(Shown 001B)
(Shown Low)
X+
X–
Ref On/Off
Y+
Y–
+REF
ADC
+IN
–IN
2.5V
Reference
–REF
7.5kΩ
VBAT
2.5kΩ
Battery
On
AUX
GND
FIGURE 2. Simplified Diagram of Analog Input.
A2
A1
A0
VBAT
AUXIN
TEMP
Y–
X+
Y+
Y-POSITION X-POSITION Z1-POSITION Z2-POSITION X-DRIVERS
Y-DRIVERS
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
+IN (TEMP0)
Off
Off
Off
X–, On
X–, On
On
Off
On
Off
Y+, On
Y+, On
Off
+IN
+IN
Measure
+IN
Measure
+IN
Measure
+IN
Measure
+IN
Off
Off
Off
Off
+IN (TEMP1)
TABLE I. Input Configuration (DIN), Single-Ended Reference Mode (SER/DFR high).
A2
A1
A0
+REF
–REF
Y–
X+
Y+
Y-POSITION
X-POSITION
Z1-POSITION
Z2-POSITION
DRIVERS ON
0
0
1
1
0
1
0
0
1
1
0
1
Y+
Y+
Y+
X+
Y–
X–
X–
X–
+IN
+IN
Measure
Y+, Y–
Y+, X–
Y+, X–
X+, X–
Measure
+IN
Measure
+IN
Measure
TABLE II. Input Configuration (DIN), Differential Reference Mode (SER/DFR low).
TSC2046
SBAS265C
9
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