CS also puts the TSC2046 into power-down mode. When
CS goes high, the TSC2046 immediately goes into power-
down mode and does not complete the current conversion.
The internal reference, however, does not turn off with CS
going high. To turn the reference off, an additional write is
required before CS goes high (PD1 = 0).
power dissipation through the bypass capacitors when the
TSC2046 is in power-down mode.
A bypass capacitor is generally not needed on the VREF pin
because the internal reference is buffered by an internal op
amp. If an external reference voltage originates from an op amp,
make sure that it can drive any bypass capacitor that is used
without oscillation.
When the TSC2046 first powers up, the device draws about
20µA of current until a control byte is written to it with PD0 = 0
to put it into power-down mode. This can be avoided if the
TSC2046 is powered up with CS = 0 and DCLK = IOVDD.
The TSC2046 architecture offers no inherent rejection of
noise or voltage variation in regards to using an external
reference input. This is of particular concern when the refer-
ence input is tied to the power supply. Any noise and ripple
from the supply appears directly in the digital results. Whereas
high-frequency noise can be filtered out, voltage variation due
to line frequency (50Hz or 60Hz) can be difficult to remove.
LAYOUT
The following layout suggestions provide the most optimum
performance from the TSC2046. Many portable applications,
however, have conflicting requirements concerning power,
cost, size, and weight. In general, most portable devices
have fairly clean power and grounds because most of the
internal components are very low power. This situation means
less bypassing for the converter power and less concern
regarding grounding. Still, each situation is unique and the
following suggestions should be reviewed carefully.
The GND pin must be connected to a clean ground point. In
many cases, this is the analog ground. Avoid connections
which are too near the grounding point of a microcontroller or
digital signal processor. If needed, run a ground trace directly
from the converter to the power-supply entry or battery-
connection point. The ideal layout includes an analog ground
plane dedicated to the converter and associated analog
circuitry.
For optimum performance, care should be taken with the
physical layout of the TSC2046 circuitry. The basic SAR
architecture is sensitive to glitches or sudden changes on the
power supply, reference, ground connections, and digital
inputs that occur just prior to latching the output of the analog
comparator. Therefore, during any single conversion for an
n-bitSAR converter, there are n ‘windows’ in which large
external transient voltages can easily affect the conversion
result. Such glitches can originate from switching power
supplies, nearby digital logic, and high-power devices. The
degree of error in the digital output depends on the reference
voltage, layout, and the exact timing of the external event.
The error can change if the external event changes in time
with respect to the DCLK input.
In the specific case of use with a resistive touch screen, care
should be taken with the connection between the converter
and the touch screen. Although resistive touch screens have
fairly low resistance, the interconnection should be as short
and robust as possible. Longer connections are a source of
error, much like the on-resistance of the internal switches.
Likewise, loose connections can be a source of error when
the contact resistance changes with flexing or vibrations.
As indicated previously, noise can be a major source of error
in touch screen applications (e.g., applications that require a
backlit LCD panel). This EMI noise can be coupled through
the LCD panel to the touch screen and cause “flickering” of
the converted data. Several things can be done to reduce
this error, such as using a touch screen with a bottom-side
metal layer connected to ground to shunt the majority of
noise to ground. Additionally, filtering capacitors from Y+,
Y–, X+, and X– pins to ground can also help. Caution should
be observed under these circumstances for settling time of
the touch screen, especially operating in the single-ended
mode and at high data rates.
With this in mind, power to the TSC2046 should be clean
and well bypassed. A 0.1µF ceramic bypass capacitor should
be placed as close to the device as possible. A 1µF to 10µF
capacitor may also be needed if the impedance of the
connection between +VCC or IOVDD and the power supplies
is high. Low-leakage capacitors should be used to minimize
TSC2046
SBAS265C
17
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