Digital Timing
POWER DISSIPATION
Figures 9 and 12 and Table VI provide detailed timing for the
digital interface of the TSC2046.
There are two major power modes for the TSC2046: full-power
(PD0 = 1) and auto power-down (PD0 = 0). When operating at
full speed and 16 clocks-per-conversion (see Figure 11), the
TSC2046 spends most of the time acquiring or converting.
There is little time for auto power-down, assuming that this
mode is active. Therefore, the difference between full-power
mode and auto power-down is negligible. If the conversion rate
15 Clocks-per-Conversion
(1)
FS = Full-Scale Voltage = VREF
1LSB = VREF(1)/4096
1LSB
11...111
1000
11...110
11...101
fCLK = 16 • fSAMPLE
100
00...010
00...001
00...000
fCLK = 2MHz
Supply Current from
+VCC and IOVDD
10
TA = 25°C
0V
FS – 1LSB
+VCC = 2.7V
Input Voltage(2) (V)
IOVDD = 1.8V
1
NOTES: (1) Reference voltage at converter: +REF – (–REF), see Figure 2.
(2) Input voltage at converter, after multiplexer: +IN – (–IN), see Figure 2
1k
10k
100k
1M
fSAMPLE (Hz)
FIGURE 14. Ideal Input Voltages and Output Codes.
FIGURE 15. Supply Current versus Directly Scaling the Fre-
quency of DCLK with Sample Rate or Maintain-
ing DCLK at the Maximum Possible Frequency.
Figure 13 provides the fastest way to clock the TSC2046.
This method does not work with the serial interface of most
microcontrollers and digital signal processors, as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method can be used with field pro-
grammable gate arrays (FPGAs) or application specific inte-
grated circuits (ASICs). Note that this effectively increases
the maximum conversion rate of the converter beyond the
values given in the specification tables, which assume 16
clock cycles per conversion.
is decreased by slowing the frequency of the DCLK input, the
two modes remain approximately equal. However, if the DCLK
frequency is kept at the maximum rate during a conversion but
conversions are done less often, the difference between the
two modes is dramatic.
Figure 15 shows the difference between reducing the DCLK
frequency (scaling DCLK to match the conversion rate) or
maintaining DCLK at the highest frequency and reducing the
number of conversions per second. In the latter case, the
converter spends an increasing percentage of time in power-
down mode (assuming the auto power-down mode is active).
Data Format
The TSC2046 output data is in Straight Binary format, as
shown in Figure 14. This figure shows the ideal output code
for the given input voltage and does not include the effects
of offset, gain, or noise.
Another important consideration for power dissipation is the
reference mode of the converter. In the single-ended refer-
ence mode, the touch panel drivers are ON only when the
analog input voltage is being acquired (see Figure 9 and
Table I). The external device (e.g., a resistive touch screen),
therefore, is only powered during the acquisition period. In
the differential reference mode, the external device must be
powered throughout the acquisition and conversion periods
(see Figure 9). If the conversion rate is high, this could
substantially increase power dissipation.
8-Bit Conversion
The TSC2046 provides an 8-bit conversion mode that can be
used when faster throughput is needed and the digital result
is not as critical. By switching to the 8-bit mode, a conversion
is complete four clock cycles earlier. Not only does this shorten
each conversion by four bits (25% faster throughput), but each
conversion can actually occur at a faster clock rate. This is
because the internal settling time of the TSC2046 is not as
critical—settling to better than 8 bits is all that is needed. The
clock rate can be as much as 50% faster. The faster clock rate
and fewer clock cycles combine to provide a 2x increase in
conversion rate.
TSC2046
16
SBAS265C
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