clocked out of the TSC2046.
+VCC • 2.7V,
+VCC • IOVDD • 1.5V,
CLOAD = 50pF
It is recommended that the processor mask the interrupt
PENIRQ is associated with whenever the processor sends a
control byte to the TSC2046. This prevents false triggering
of interrupts when the PENIRQ output is disabled in the
cases discussed in this section.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tACQ
tDS
Acquisition Time
1.5
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DIN Valid Prior to DCLK Rising 100
tDH
DIN Hold After DCLK High
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
50
16 Clocks-per-Conversion
tDO
tDV
200
200
200
The control bits for conversion n + 1 can be overlapped with
conversion n to allow for a conversion every 16 clock cycles,
as shown in Figure 11. This figure also shows possible serial
communication occurring with other serial peripherals be-
tween each byte transfer from the processor to the con-
verter. This is possible, provided that each conversion com-
pletes within 1.6ms of starting. Otherwise, the signal that is
captured on the input sample-and-hold may droop enough to
affect the conversion result. Note that the TSC2046 is fully
powered while other serial communications are taking place
during a conversion.
tTR
tCSS
tCSH
tCH
CS Falling to First DCLK Rising 100
CS Rising to DCLK Ignored
DCLK High
10
200
200
tCL
DCLK Low
tBD
DCLK Falling to BUSY Rising/Falling
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
200
200
200
tBDV
tBTR
TABLE VI. Timing Specifications, TA = –40°C to +85°C.
CS
tCL
tCSH
tCSS
tCH
tBD
tBD
tDO
DCLK
DIN
tDH
tDS
PD0
tBDV
tBTR
BUSY
DOUT
tDV
tTR
11
10
FIGURE 12. Detailed Timing Diagram.
CS
Power-Down
DCLK
1
15
1
15
1
SER/
DFR
SER/
DFR
DIN
BUSY
DOUT
S
A2 A1 A0 MODE
PD1 PD0
S
A2 A1 A0 MODE
PD1 PD0
S
A2 A1 A0
11 10
9
8
7
6
5
4
3
2
1
0
11 10
9
8
7
FIGURE 13. Maximum Conversion Rate, 15 Clocks-per-Conversion.
TSC2046
SBAS265C
15
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