PCM3793A
PCM3794A
www.ti.com
SLAS529A–JANUARY 2007–REVISED FEBRUARY 2007
PCM3793A/94A DESCRIPTION
Analog Input
The AIN1L, AIN1R, AIN2L, AIN2R, AIN3L, and AIN3R pins can be used as microphone or line inputs with
selectable 0- or 20-dB boost and 1-Vrms input. All of these analog inputs have high input impedance (20 kΩ),
which is not changed by gain settings. One pair of inputs is selected by register 87 (AIL[1:0], AIR[1:0]). AIN1L
and AIN1R can be used as a monaural differential input.
Gain Settings for Analog Input
The gain of the analog signals can be adjusted from 30 dB to –12 dB in 1-dB steps following the 0- or 20-dB
boost amplifier. The gain level can be set for each channel by registers 79 and 80 (ALV[5:0], ARV[5:0]).
A/D Converter
The ADC includes a multilevel delta-sigma modulator, aliasing filter, decimation filter, high-pass filter, and notch
filter and can accept a 1-Vrms full-scale voltage input. The decimation filter has a digital soft mute controlled by
register 81 (RMUL, RMUR). The high-pass filter can be disabled by register 81 (HPF[1:0]), and the notch filter
can be disabled by registers 96 to 104 if it is not necessary to cancel a dc offset or compensate for wind noise.
D/A Converter
The DAC includes a multilevel delta-sigma modulator and an interpolation filter. These can be used to obtain
high PSRR, low jitter sensitivity, and low out-of-band noise quickly and easily. The interpolation filter includes
digital attenuator, digital soft mute, three-band tone control (bass, midrange and treble), and 3-D sound
controlled by registers 92 to 95. The de-emphasis filter (32, 44.1 and 48 kHz) is controlled by registers 68 to 70
(ATL[5:0], ATR[5:0], PMUL, PMUR, DEM[1:0]). Oversampling rate control can reduce out-of-band noise when
operating at low sampling rates by using register 70 (OVER).
Common Voltage
The VCOM pin is normally biased to 0.5 VCC, and it provides the common voltage to internal circuitry. It is
recommended that a 4.7-µF capacitor be connected between this pin and AGND to provide clean voltage and
avoid pop noise. The PCM3793A/94A may have a little pop noise on each analog output if a capacitor smaller
than 4.7 µF is used.
Line Output
The HPOL/LOL, HPOR/LOR, and HPCOM/MONO pins can drive a 10-kΩ load and be configured by register 74
(HPS[1:0]) as a monaural single-ended, monaural differential, or stereo single-line output with 1-Vrms output.
These outputs, except for the HPCOM/MONO pin, include an analog volume amplifier that can be set from 6 dB
to –70 dB and mute in steps of 0.5-, 1-, 2- or 4-dB. Each output is controlled by registers 64 and 65 (HLV[5:0],
HRV[5:0], HMUL, HMUR). No dc blocking capacitor is required when connecting an external speaker amplifier
with monaural differential input. The center voltage is 0.5 VCC with zero data input.
Headphone Output
The HPOL/LOL, HPOR/LOR, and HPCOM/MONO pins can be configured as a stereo, monaural, or monaural
differential headphone output by register 74 (HPS[1:0]). These pins have more than 30 or 40 mWrms output
power into a 32- or 16-Ω load, either through a dc blocking capacitor or without a capacitor. These outputs,
except for the HPCOM/MONO pin, include an analog volume amplifier that can be set from 6 dB to –70 dB in
steps of 0.5, 1, 2, or 4 dB. Each is controlled by registers 64 and 65 (HLV[5:0], HRV[5:0], HMUL, HMUR). The
center voltage is 0.5 VCC with zero data input.
Headphone Plug Insertion Detection
The HDTI pin detects the insertion status of headphone plug and writes the status to register 77 (HPDS), which
can be read by the I2C interface. The polarity of the status indication can be inverted by register 75 (HPDP). The
headphone and speaker amplifiers are disabled or enabled automatically by headphone plug
insertion/extractrion if register 75, HPDE = 1. They follow the register settings if register 75, HPDE = 0.
HPCOM/MONO is not affected by the status when register 74, CMS[0] = 1.
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