constant and can be driven by either a voltage or current, AC
or DC, positive or negative polarity, and have a voltage range
up to ±20V.
DISCUSSION OF
SPECIFICATIONS
RELATIVE ACCURACY
This term, also known as end point linearity or integral
linearity, describes the transfer function of analog output to
digital input code. Relative accuracy describes the deviation
from a straight line, after zero and full-scale errors have been
adjusted to zero.
VREF A
R
R
R
RFB A
R
2R
2R
2R
2R
2R
IOUT A
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the deviation from an ideal 1LSB
change in the output when the input code changes by 1LSB.
A differential nonlinearity specification of 1LSB maximum
ensures monotonicity.
AGND
DB11
(MSB)
DB10
DB9
DB0
(LSB)
FIGURE 1. Simplified Circuit Diagram for DAC A.
GAIN ERROR
Gain error is the difference between the full-scale DAC output
and the ideal value. The ideal full scale output value for the
DAC780x is –(4095/4096)VREF. Gain error may be adjusted
to zero using external trims, see Figures 5 and 7.
A CMOS switch transistor, included in series with the ladder
terminating resistor and in series with the feedback resistor,
RFB A, compensates for the temperature drift of the ON resis-
tance of the ladder switches.
OUTPUT LEAKAGE CURRENT
Figure 2 shows an equivalent circuit for DAC A. COUT is the
output capacitance due to the N-channel switches and varies
from about 30pF to 70pF with digital input code. The current
source ILKG is the combination of surface and junction leak-
ages to the substrate. ILKG approximately doubles every 10°C.
RO is the equivalent output resistance of the DAC and it varies
with input code.
The current which appears at IOUT A and IOUT B with the DAC
loaded with all zeros.
OUTPUT CAPACITANCE
The parasitic capacitance measured from IOUT A or IOUT B to
AGND.
CHANNEL-TO-CHANNEL ISOLATION
The AC output error due to capacitive coupling from DAC A
to DAC B or DAC B to DAC A.
R
RFB A
IOUT A
VREF A
MULTIPLYING FEEDTHROUGH ERROR
ILKG
DIN VREF
COUT
RO
x
R
The AC output error due to capacitive coupling from VREF to
4096
R
I
OUT with the DAC loaded with all zeros.
AGND A
OUTPUT CURRENT SETTLING TIME
FIGURE 2. Equivalent Circuit for DAC A.
The time required for the output current to settle to within
+0.01% of final value for a full-scale step.
INSTALLATION
DIGITAL-TO-ANALOG GLITCH ENERGY
The integrated area of the glitch pulse measured in nanovolt-
seconds. The key contributor to DAC glitch is charge injected
by digital logic switching transients.
ESD PROTECTION
All digital inputs of the DAC780x incorporate on-chip ESD
protection circuitry. This protection is designed to withstand
2.5kV (using the Human Body Model, 100pF and 1500Ω).
However, industry standard ESD protection methods should
be used when handling or storing these components. When
not in use, devices should be stored in conductive foam or
rails. The foam or rails should be discharged to the destina-
tion socket potential before devices are removed.
DIGITAL CROSSTALK
Glitch impulse measured at the output of one DAC but caused
by a full-scale transition on the other DAC. The integrated
area of the glitch pulse is measured in nanovolt-seconds.
CIRCUIT DESCRIPTION
POWER-SUPPLY CONNECTIONS
Figure1showsasimplifiedschematicofonehalfofaDAC780x.
The current from the VREF A pin is switched between IOUT A and
AGND by 12 single-pole double-throw CMOS switches. This
maintains a constant current in each leg of the ladder regard-
less of the input code. The input resistance at VREF is therefore
The DAC780x are designed to operate on VDD = +5V +10%.
For optimum performance and noise rejection, power-supply
decoupling capacitors CD should be added as shown in the
application circuits. These capacitors (1µF tantalum recom-
mended) should be located close to the DAC. AGND and
DAC7800, 7801, 7802
8
SBAS005A
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