DAC7801
BLOCK DIAGRAM
V
DD
20
PIN CONFIGURATION
Top View
DIP
DAC7801
DAC A
MS
Input
Reg
4
DAC A
LS
Input
Reg
AGND A
I
OUT A
1
2
3
4
5
6
DAC7801
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
AGND B
I
OUT B
R
FB B
V
REF B
V
DD
UPD
WR
CLR
A1
A0
DB7
DB6
8
DAC A Register
12
UPD
A1
A0
CS
WR
CLR
19
DAC A
2
1
3
I
OUT A
AGND A
R
FB A
V
REF A
V
REF B
R
FB B
I
OUT B
AGND B
R
FB A
V
REF A
CS
DB0
DB1
DB2
DB3
DB4
DB5
DGND
Control Logic
16
15
5
18
17
4
21
22
DAC B
12
DAC B Register
4
DAC B
MS
Input
Reg
8
DAC B
LS
Input
Reg
23
24
14
6
12
DGND
DB7–DB0
LOGIC TRUTH TABLE
CLR
1
1
0
1
1
1
1
1
1
X = Don’t care.
UPD
1
1
X
1
1
1
1
0
0
CS
1
X
X
0
0
0
0
1
0
WR
X
1
X
0
0
0
0
0
0
A1
X
X
X
0
0
1
1
X
X
A0
X
X
X
0
1
0
1
X
X
FUNCTION
No Data Transfer
No Data Transfer
All Registers Cleared
DAC A LS Input Register Loaded with DB7 - DB0 (LSB)
DAC A MS Input Register Loaded with DB3 (MSB) - DB0
DAC B LS Input Register Loaded with DB7 - DB0 (LSB)
DAC B MS Input Register Loaded with DB3 (MSB) - DB0
DAC A, DAC B Registers Updated Simultaneously from Input Registers
DAC A, DAC B Registers are Transparent
TIMING CHARACTERISTICS
V
DD
= +5V, V
REF A
= V
REF B
= +10V, T
A
= –40°C to +85°C.
t
1
A0–A1
t
3
t
4
t
6
t
7
WR
t
8
CLR
t
2
5V
0V
5V
0V
5V
0V
5V
0V
5V
0V
PARAMETER
t
1
— Address Valid to Write Setup Time
t
2
— Address Valid to Write Hold Time
t
3
— Data Setup Time
t
4
— Data Hold Time
t
5
— Chip Select or Update to Write Setup Time
t
6
— Chip Select or Update to Write Hold Time
t
7
— Write Pulse Width
t
8
— Clear Pulse Width
MINIMUM
10ns
10ns
30ns
10ns
0ns
0ns
40ns
40ns
DATA
t
5
CS, UPD
NOTES: (1) All input signal rise and fall times are measured from 10% to 90%
of +5V. t = t = 5ns. (2) Timing measurement reference level is V
IH
+ V
IL
.
R
F
2
DAC7800, 7801, 7802
SBAS005A
www.ti.com
5
BURR-BROWN [ BURR-BROWN CORPORATION ]
