DAC7800 (Cont.)
DATA INPUT FORMAT
DAC7800 Digital Interface Block Diagram
UPD B
UPD A
LSB
DAC A Register
DAC B Register
MSB
LSB
MSB
CLK
Bit
Bit
12
Bit
11
Bit
0
24-Bit
Shift Register
23
Data In
DAC7800 Data Input Sequence
CLK
Data In
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Bit 17 Bit 18 Bit 19 Bit 20 Bit 21 Bit 22 Bit 23
MSB
LSB MSB
LSB
DAC B
DAC B DAC A
DAC A
TIMING CHARACTERISTICS
VDD = +5V, VREF A = VREF B = +10V, TA = –40°C to +85°C.
t5
CLK
0V
PARAMETER
MINIMUM
t1
t1 — Data Setup Time
t2 — Data Hold Time
t3 — Chip Select to CLK,
Update, Data Setup Time
t4 — Chip Select to CLK,
Update, Data Hold Time
t5 — CLK Pulse Width
t6 — Clear Pulse Width
t7 — Update Pulse Width
t8 — CLK Edge to UPD A
or UPD B
15ns
15ns
15ns
5V
0V
DATA
CS
t3
t2
5V
40ns
t8
t7
t4
5V
5V
UPD A
UPD B
40ns
40ns
40ns
15ns
t6
CLR
NOTES: (1) All input signal rise and fall times are measured from 10% to 90% of +5V. tR = tF = 5ns.
VIH+ VIL
.
(2) Timing measurement reference level is
2
DAC7800, 7801, 7802
4
SBAS005A
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