DIGITAL TIMING
V
REFH – VREFL • N
(
)
Figure 14 and Table II provide detailed timing for the digital
interface of the DAC7644.
VOUT = VREFL +
(1)
65,536
DIGITAL INPUT CODING
where N is the digital input code. This equation does not
include the effects of offset (zero-scale) or gain (full-scale)
errors.
The DAC7644 input data is in Straight Binary format. The
output voltage is given by Equation 1.
tWCS
CS
tWS
tWH
R/W
tRCS
tAH
CS
tAS
tRDH
tRDS
A0/A1
tLH
R/W
tLS
tLWD
tLX
tAS
tAH
±0.003% of FSR
Error Band
LOADDACS
Data In
A0/A1
tDH
tDS
tDZ
tS
Data Out
Data Valid
tCSD
VOUT
Data Read Timing
Data Write Timing
±0.003% of FSR
Error Band
tSS
tSH
RESET SEL
tRSH
tRSS
RST
+FS
VOUT,RESET SEL LOW
–FS
+FS
MS
VOUT,RESET SEL HIGH
–FS
DAC7644 Reset Timing
FIGURE 14. Digital Input and Output Timing.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tRCS
tRDS
tRDH
tDZ
tCSD
tWCS
tWS
tWH
tAS
tAH
tLS
tLH
tLX
tDS
tDH
tLWD
tSS
tSH
tRSS
tRSH
tS
CS LOW for Read
R/W HIGH to CS LOW
R/W HIGH after CS HIGH
CS HIGH to Data Bus in High Impedance
CS LOW to Data Bus Valid
CS LOW for Write
150
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
10
100
150
100
40
0
10
0
10
30
100
100
0
10
100
0
R/W LOW to CS LOW
R/W LOW after CS HIGH
Address Valid to CS LOW
Address Valid after CS HIGH
CS LOW to LOADDACS HIGH
CS LOW after LOADDACS HIGH
LOADDACS HIGH
Data Valid to CS LOW
Data Valid after CS HIGH
LOADDACS LOW
RSTSEL Valid Before RESET HIGH
RSTSEL Valid After RESET HIGH
RESET LOW Before RESET HIGH
RESET LOW After RESET HIGH
Settling Time
200
10
10
10
TABLE II. Timing Specifications (TA = –40°C to +85°C).
®
20
DAC7644
BB [ BURR-BROWN CORPORATION ]
