LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
LINEARITY ERROR AND
DIFFERENTIAL LINEARITY ERROR vs CODE
(DAC A, +25°C)
2.5
2.0
3.0
2.5
2.0
1.5
1.0
0.5
0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–0.5
–1.0
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH
Digital Input Code
Digital Input Code
FIGURE 13. Linearity and Differential Linearity Error Curves
for Figure 12.
FIGURE 11. Linearity and Differential Linearity Error Curves
for Figure 10.
DIGITAL INTERFACE
Table I shows the basic control logic for the DAC7644. Note
that each internal register is edge triggered and not level
triggered. When the LOADDACS signal is transitioned to
HIGH, the digital word currently in the register is latched.
The first set of registers (the input registers) are triggered via
the A0, A1, R/W, and CS inputs. Only one of these registers
is transparent at any given time.
NC 48
NC 47
NC 46
NC 45
V
OUTA Sense 44
OUTA 43
REFL AB Sense 42
REFL AB 41
REFH AB 40
REFH AB Sense 39
OUTB Sense 38
OUTB 37
VOUT
V
DAC7644
The double-buffered architecture is designed mainly so each
DAC input register can be written to at any time and then all
DAC voltages updated simultaneously by the rising edge of
LOADDACS. It also allows a DAC input register to be
written to at any point and the DAC voltages to be synchro-
nously changed via a trigger signal connected to
LOADDACS.
V
+V
V
+2.5V
V
V
V
VOUT
V
FIGURE 12. Low Cost Single-Supply Configuration.
INPUT
DAC
A1
A0
R/W
CS
RST
RSTSEL LOADDACS
REGISTER
REGISTER
MODE
DAC
L
L
H
H
L
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
X
X
H
H
H
H
H
H
H
H
H
H
↑
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
↑
Write
Write
Write
Write
Read
Read
Read
Read
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Hold
Write
Write Input
Write Input
Write Input
Write Input
Read Input
Read Input
Read Input
Read Input
Update
A
B
C
D
A
B
C
D
All
All
All
All
L
H
H
H
H
X
X
X
X
L
H
L
H
H
X
X
X
X
H
X
X
X
X
H
X
X
Hold
Hold
Hold
Reset to Zero
Reset to Midscale
Reset to Zero
Reset to Midscale
↑
H
TABLE I. DAC7644 Logic Truth Table.
®
19
DAC7644
BB [ BURR-BROWN CORPORATION ]
