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DAC7614E 参数 Datasheet PDF下载

DAC7614E图片预览
型号: DAC7614E
PDF下载: 下载PDF文件 查看货源
内容描述: 四,串行输入, 12位电压输出数位类比转换器 [Quad, Serial Input, 12-Bit, Voltage Output DIGITAL-TO-ANALOG CONVERTER]
分类和应用: 转换器数模转换器光电二极管信息通信管理
文件页数/大小: 12 页 / 486 K
品牌: BB [ BURR-BROWN CORPORATION ]
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Note that CS and CLK are combined with an OR gate and  
the output controls the serial-to-parallel shift register inter-  
nal to the DAC7614 (see the block diagram on the front of  
this data sheet). These two inputs are completely inter-  
changeable. In addition, care must be taken with the state of  
CLK when CS rises at the end of a serial transfer. If CLK is  
LOW when CS rises, the OR gate will provide a rising edge  
to the shift register, shifting the internal data one additional  
bit. The result will be incorrect data and possible selection of  
the wrong DAC.  
STATE OF  
SELECTED  
DAC  
SELECTED  
DAC  
REGISTER  
A1  
A0  
LOADDACS RESET  
REGISTER  
L(1)  
L
L
H
L
L
L
H
H
H
H
H
L
A
B
Transparent  
Transparent  
Transparent  
Transparent  
(All Latched)  
Reset(3)  
H
L
C
H
H
X
X
L
D
X(2)  
X
H
X
NONE  
ALL  
NOTES: (1) L = Logic LOW. (2) X = Don’t Care. (3) Resets to either 000H or  
800H, per the RESETSEL state (LOW = 000H, HIGH = 800H). When RESET  
rises, all registers that are in their latched state retain the reset value.  
If both CS and CLK are used, then CS should rise only when  
CLK is HIGH. If not, then either CS or CLK can be used to  
operate the shift register. See Table III for more information.  
TABLE II. Control Logic Truth Table.  
Digital Input Coding  
CS(1)  
CLK(1) LOADDACS  
RESET  
SERIAL SHIFT REGISTER  
The DAC7614 input data is in Straight Binary format. The  
output voltage is given by the following equation:  
H(2)  
L(4)  
L
X(3)  
L
H
H
H
H
No Change  
No Change  
(VREFH – VREFL) • N  
(5)  
H
H
Advanced One Bit  
Advanced One Bit  
No Change  
VOUT = VREFL  
+
4096  
L
X
X
H
H
H(6)  
H(6)  
L(7)  
H
H
where N is the digital input code (in decimal). This equation  
does not include the effects of offset (zero-scale) or gain  
(full-scale) errors.  
L(8)  
No Change  
NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X =  
Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH  
value is suggested in order to avoid a “false clock” from advancing the shift  
register and changing the shift register. (7) If data is clocked into the serial  
register while LOADDACS is LOW, the selected DAC register will change as  
the shift register bits “flow” through A1 and A0. This will corrupt the data in  
each DAC register that has been erroneously selected. (8) RESET LOW  
causes no change in the contents of the serial shift register.  
TABLE III. Serial Shift Register Truth Table.  
®
11  
DAC7614