REFERENCE INPUTS
SYMBOL
DESCRIPTION
MIN
TYP MAX UNITS
The reference inputs, VREFL and VREFH, can be any voltage
between VSS + 2.25V and VDD – 2.25V provided that
VREFH is at least 1.25V greater than VREFL. The minimum
output of each DAC is equal to VREFL – 1LSB plus a small
offset voltage (essentially, the offset of the output op amp).
The maximum output is equal to VREFH plus a similar
offset voltage. Note that VSS (the negative power supply)
must either be connected to ground or must be in the range
of –4.75V to –5.25V. The voltage on VSS sets several bias
points within the converter. If VSS is not in one of these two
configurations, the bias values may be in error and proper
operation of the device is not guaranteed.
tDS
Data Valid to CLK Rising
Data Held Valid after CLK Rises
CLK HIGH
25
20
30
50
55
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
tDH
tCH
tCL
CLK LOW
tCSS
tCSH
tLD1
tLD2
tLDDW
tRSSH
tRSTW
tS
CS LOW to CLK Rising
CLK HIGH to CS Rising
LOADDACS HIGH to CLK Rising 40
CLK Rising to LOADDACS LOW
LOADDACS LOW Time
RESETSEL Valid to RESET LOW
RESET LOW Time
15
45
25
70
10
Settling Time
The current into the reference inputs depends on the DAC
output voltages and can vary from a few microamps to
approximately 0.6 milliamp. Bypassing the reference volt-
age or voltages with a 0.1µF capacitor placed as close as
possible to the DAC7614 package is strongly recommended.
TABLE I. Timing Specifications (TA = –40°C to +85°C).
asynchronous reset input (RESET) is provided to simplify
start-up conditions, periodic resets, or emergency resets to a
known state.
DIGITAL INTERFACE
The DAC code and address are provided via a 16-bit serial
interface as shown in Figure 3. The first two bits select the
DAC register that will be updated when LOADDACS goes
LOW (see Table II). The next two bits are not used. The last
12 bits is the DAC code which is provided, most significant
bit first.
Figure 3 and Table I provide the basic timing for the
DAC7614. The interface consists of a serial clock (CLK),
serial data (SDI), and a load DAC signal (LOADDACS). In
addition, a chip select (CS) input is available to enable serial
communication when there are multiple serial devices. An
(MSB)
(LSB)
SDI
A1
A0
X
X
D11
D10
D9
D3
D2
D1
D0
CLK
CS
tCSH
t
css
tLD2
tLD1
LOADDAC
tLDDW
tDS
tDH
SDI
tCL
tCH
CLK
tLDDW
LOADDAC
VOUT
tS
tS
1 LSB
ERROR BAND
1 LSB
ERROR BAND
tRSTW
RESET
tRSSH
RESETSEL
FIGURE 3. DAC7614 Timing.
®
10
DAC7614
BB [ BURR-BROWN CORPORATION ]
