ADS7863
www.ti.com
SBAS383–JUNE 2007
Additionally, the SDI pin is used for controlling device
functionality; see the Serial Data Input section for
details.
16 clock cycles are required to perform a single
conversion. With the rising edge of CONVST, the
ADS7863 switches asynchronously to the external
CLOCK from sample to hold mode.
Converted data on the SDOx pins becomes valid
with the third falling CLOCK edge after generating an
RD pulse. The following sections explain the four
different modes of operation in detail.
After some delay (t12), the BUSY output pin goes
high and remains high for the duration of the
conversion cycle. On the falling edge of the second
CLOCK cycle, the ADS7863 latches in the channel
for the next conversion cycle, depending on the
status of the SDI pin. CS must be brought low to
enable both serial outputs. Data are valid on the
falling edge of every 16 clock cycles per conversion.
The first two bits are set to '0'. The subsequent data
contain the 12-bit conversion result (the most
significant bit is transferred first), followed by two '0's
(see Figure 1 and Figure 16).
MODE I
With the M0 and M1 pins both set to '0', the
ADS7863 enters manual channel control operation.
The SDI pin is used to switch between the channels.
A conversion is initiated by bringing CONVST high.
1
16
1
16
CLOCK
CONVST
SDI
C[1:0] = '11' ® Convert CHx1 Next
C[1:0] = '00' ® Convert CHx0 Next
P[1:0] = '00' ® SDI Features Not Used
C[1:0] = '00' ® Convert CHx0 Next
P[1:0] = '11' ® SDI Features Not Used
P[1:0] = '00' ® SDI Features Not Used
M0
M1
RD
CS
High-Z
High-Z
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SDOA
Previous 12-Bit Data CHAx
12-Bit Data CHA1
0
SDOB
BUSY
Previous 12-Bit Data CHBx
12-Bit Data CHB1
Previous Conversion of Both CHxx
Conversion of Both CHx1
Conversion of Both CHx0
0ms
0.5ms
1.0ms
Figure 16. Mode I Timing Diagram (M0 = 0; M1 = 0)
14
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