ADS7863
www.ti.com
SBAS383–JUNE 2007
APPLICATIONS INFORMATION
GENERAL DESCRIPTION
CHx1+
The ADS7863 includes two 12-bit analog-to-digital
converters (ADCs) that operate based on the
successive-approximation register (SAR) principle.
The ADCs sample and convert simultaneously.
Conversion time can be as low as 541.67ns. Adding
the acquisition time of 125ns results in a maximum
conversion rate of 1.5MSPS.
CHx1-
ADC+
ADC-
Input
MUX
CHx0+
CHx0-
Figure 15. Input Multiplexer Configuration
Each ADC has a fully differential, 2:1 multiplexer
front-end. In many common applications, all negative
input signals remain at the same constant voltage
(for example, 2.5V). In this type of application, the
multiplexer can be used in a pseudo-differential 3:1
mode, where CHx0– functions as a common pin and
the remaining three inputs (CHx0+, CHx1–, and
CHx1+) operate as separate inputs referred to the
common pin.
Table 1. Fully Differential 2:1 Multiplexer
Configuration
C1
0
C0
0
ADC+
CHx0+
CHx1+
ADC–
CHx0–
CHx1–
1
1
Table 2. Pseudo-Differential 3:1 Multiplexer
Configuration
The ADS7863 also includes
reference. The reference
a
2.5V internal
drives 10-bit
a
C1
0
C0
0
ADC+
CHx0+
CHx1–
CHx1+
ADC–
CHx0–
CHx0–
CHx0–
digital-to-analog converter (DAC), allowing the
voltage at the REFOUT pin to be adjusted via the
0
1
serial interface in 2.44mV steps.
A low-noise
1
1
operational amplifier with unity gain buffers the DAC
output voltage and drives the REFOUT pin.
Each of the of 2pF sample-and-hold capacitors
(shown as CS in the Equivalent Input Circuit) is
connected via switches to the multiplexer output.
Opening the switches holds the sampled data during
the conversion process. After finishing the
conversion, both capacitors are pre-charged for the
duration of one clock cycle to the voltage present at
the REFIN pin. After the pre-charging, the multiplexer
outputs are connected to the sampling capacitors
again. The voltage at the analog input pin is usually
different from the reference voltage; therefore, the
sample capacitors must be charged to within
one-half LSB for 12-bit accuracy during the
The ADS7863 offers a serial interface that is
compatible with the ADS7861. However, instead of
the A0 pin of the ADS7861 that controls the channel
selection, the ADS7863 offers a serial data input
(SDI) pin that supports additional functions described
in the Digital section of this data sheet.
ANALOG
This section addresses the analog input circuit, the
ADCs, and the reference design of the device.
Analog Inputs
acquisition
time
tACQ
(see
the
Timing
Characteristics).
Each ADC is fed by an input multiplexer; see
Figure 15. Each multiplexer is either used in a
fully-differential 2:1 configuration (as described in
Table 1) or a pseudo-differential 3:1 configuration (as
shown in Table 2). The channel selection is
performed using bits C1 and C0 in the SDI Register
(see also the Serial Data Input section).
Acquisition time is indicated with the BUSY signal
being held low. It starts by closing the input switches
(after finishing the previous conversion and
pre-charging) and finishes with the rising edge of the
CONVST signal. If the ADS7863 operates at full
speed, the acquisition time is typically 125ns.
The input path for the converter is fully differential
and provides a common-mode rejection of 80dB at
50kHz. The high CMRR also helps suppress noise in
harsh industrial environments.
The minimum –3dB bandwidth of the driving
operational amplifier can be calculated as shown in
Equation 1, with n = 12 being the resolution of the
ADS7863:
ln(2) ´ (n + 1)
f
=
-3dB
2p ´ tACQ
(1)
11
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