ADS7863
www.ti.com
SBAS383–JUNE 2007
For operation with a 2.7V analog supply and a 2.5V
reference, the internal reference buffer requires a
rail-to-rail input and output. Such buffers typically
contain two input stages; when the input voltage
passes the mid-range area, a transition occurs at the
output because of switching between the two input
stages. In this voltage range, rail-to-rail amplifiers
generally show a very poor power-supply rejection.
AN: AutoNap power-down enable ('1' = device in
AutoNap power-down mode)
RP: Reference power-down ('1' = reference
turned off)
S4: Special read mode for Modes II and IV
('1' = special mode enabled)
Table 6. A2, A1, and A0: DAC Control and Device
Reset
As a result of this poor performance, the ADS7863
buffer has a fixed transition at DAC code 496
(0x1F0). At this code, the DAC may show a jump of
up to 10mV in its transfer function.
A2
0
A1
0
A0
0
FUNCTION
No action
0
0
1
DAC write with next access
No action
0
1
0
DIGITAL
0
1
1
DAC read with next access
No action
This section addresses the timing and control of the
ADS7863 serial interface.
1
0
0
1
0
1
Device reset
1
1
0
No action
Serial Data Input (SDI)
1
1
1
No action
The serial data input or SDI pin (corresponding to pin
A0 on the ADS7861) is coupled to RD and clocked
into the ADS7863 on each falling edge of CLOCK.
The data word length of the SDI Register is 12 bits.
Table 3 shows the register structure. The data must
be transferred MSB-first. Table 4 through Table 6
describe specific bits of this register. The default
value of this register after power-up is 0x000.
All additional features become active with the rising
edge of the 12th CLOCK signal after issuing the RD
pulse.
Timing and Control
IMPORTANT:
Consider the Detailed Timing Diagram (Figure 1)
and CONVST timing diagram (Figure 2) shown in
the Timing Characteristics section. For maximum
data throughput, the descriptions and diagrams
given in this data sheet assume that the
CONVST and RD pins are tied together. Note
that they can also be controlled independently.
Table 3. SDI Register Contents
SDI REGISTER BIT
11 10
9
8
7
6
5
4
3
2
1
0
C1 C0 P1 P0 DP
N
AN RP S4 A2 A1 A0
Table 4. C1 and C0: Channel Selection
The operation of the ADS7863 can be configured in
four different modes by using the mode pins M0 and
M1, as shown in Table 7.
ADC A/B
C1
0
C0
0
POSITIVE INPUT
CHA0+ / CHB0+
CHA1– / CHB1–
CHA1+ / CHB1+
CHA1+ / CHB1+
NEGATIVE INPUT
CHA0– / CHB0–
CHA0– / CHB0–
CHA0– / CHB0–
CHA1– / CHB1–
Pin M0 sets either manual or automatic channel
selection. In manual mode, the SDI pin is used to
select between channels CHx0 and CHx1; in
automatic operation, the SDI pin is ignored and
channel selection is controlled by the device after
each conversion. Pin M1 selects between serial data
being transmitted simultaneously on both outputs
SDOA and SDOB for each channel respectively, or
using only the SDOA output for transmitting data
from both channels (see Figure 16 through Figure 23
and the associated text for more information).
0
1
1
0
1
1
Table 5. P1 and P0: Additional Features Enable
P1
0
P0
0
FUNCTION
Convert both CHx0 channels
Activate additional features
0
1
1
0
Reserved for factory test (do not
use)
Table 7. M1/M0 Truth Table
1
1
Convert both CHx1 channels
CHANNEL
M0
0
M1
0
SELECTION
Manual (via SDI)
Manual (via SDI)
Automatic
SDOx USED
SDOA and SDOB
SDOA only
DP: Deep power-down enable ('1' = device in
deep power-down mode)
N: Nap power-down enable ('1' = device in Nap
power-down mode)
0
1
1
0
SDOA and SDOB
SDOA only
1
1
Automatic
13
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