Figure 14 shows the difference between reducing the DCLK
frequency (scaling DCLK to match the conversion rate) or
maintaining DCLK at the highest frequency and reducing the
number of conversions per second. In the latter case, the
converter spends an increasing percentage of time in power-
down mode (assuming the auto power-down mode is active).
LAYOUT
The following layout suggestions provide the most optimum
performance from the ADS7846. However, many portable
applications have conflicting requirements concerning power,
cost, size, and weight. In general, most portable devices
have fairly clean power and grounds because most of the
internal components are very low power. This situation means
less bypassing for the converter power and less concern
regarding grounding. Still, each situation is unique and the
following suggestions should be reviewed carefully.
1000
fCLK = 16 • fSAMPLE
For optimum performance, care must be taken with the
physical layout of the ADS7846 circuitry. The basic SAR
architecture is sensitive to glitches or sudden changes on the
power supply, reference, ground connections, and digital
inputs that occur just prior to latching the output of the analog
comparator. Therefore, during any single conversion for an
n-bit SAR converter, there are n ‘windows’ in which large
external transient voltages can easily affect the conversion
result. Such glitches can originate from switching power
supplies, nearby digital logic, and high-power devices. The
degree of error in the digital output depends on the reference
voltage, layout, and the exact timing of the external event.
The error can change if the external event changes in time
with respect to the DCLK input.
100
fCLK = 2MHz
10
TA = 25°C
+VCC = +2.7V
1
1k
10k
100k
1M
f
SAMPLE (Hz)
FIGURE 14. Supply Current versus Directly Scaling the Fre-
quency of DCLK with Sample Rate or Maintain-
ing DCLK at the Maximum Possible Frequency.
With this in mind, power to the ADS7846 should be clean and
well bypassed. A 0.1µF ceramic bypass capacitor should be
placed as close to the device as possible. A 1µF to 10µF
capacitor may also be needed if the impedance of the
connection between +VCC and the power supply is high. Low-
leakage capacitors should be used to minimize power dissi-
pation through the bypass capacitors when the ADS7846 is
in power-down mode.
Another important consideration for power dissipation is the
reference mode of the converter. In the single-ended refer-
ence mode, the touch panel drivers are on only when the
analog input voltage is being acquired (see Figure 9 and
Table I). Therefore, the external device (e.g., a resistive
touch screen) is only powered during the acquisition period.
In the differential reference mode, the external device must
be powered throughout the acquisition and conversion peri-
ods (see Figure 9). If the conversion rate is high, this could
substantially increase power dissipation.
A bypass capacitor is generally not needed on the VREF pin
because the internal reference is buffered by an internal op
amp. If an external reference voltage originates from an op
amp, make sure that it can drive any bypass capacitor that
is used without oscillation.
CS also puts the ADS7846 into power-down mode. When
CS goes high, the ADS7846 immediately goes into power-
down and does not complete the current conversion. How-
ever, the internal reference does not turn off with CS going
high. To turn the reference off, an additional write is required
before CS goes high (PD1 = 0).
The ADS7846 architecture offers no inherent rejection of
noise or voltage variation in regards to using an external
reference input. This is of particular concern when the
reference input is tied to the power supply. Any noise and
ripple from the supply appears directly in the digital results.
Whereas high-frequency noise can be filtered out, voltage
variation due to line frequency (50Hz or 60Hz) can be difficult
to remove.
ADS7846
16
SBAS125H
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