16 Clocks-per-Conversion
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tACQ
tDS
Acquisition Time
1.5
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
The control bits for conversion n + 1 can be overlapped with
conversion n to allow for a conversion every 16 clock cycles,
as shown in Figure 10. This figure also shows possible serial
communication occurring with other serial peripherals be-
tween each byte transfer from the processor to the converter.
This is possible provided that each conversion completes
within 1.6ms of starting. Otherwise, the signal that is cap-
tured on the input sample-and-hold may droop enough to
affect the conversion result. Note that the ADS7846 is fully
powered while other serial communications are taking place
during a conversion.
DIN Valid Prior to DCLK Rising 100
tDH
DIN Hold After DCLK High
DCLK Falling to DOUT Valid
CS Falling to DOUT Enabled
CS Rising to DOUT Disabled
10
tDO
tDV
200
200
200
tTR
tCSS
tCSH
tCH
CS Falling to First DCLK Rising 100
CS Rising to DCLK Ignored
DCLK High
0
200
200
tCL
DCLK Low
tBD
DCLK Falling to BUSY Rising
CS Falling to BUSY Enabled
CS Rising to BUSY Disabled
200
200
200
tBDV
tBTR
Digital Timing
Figures 9, 11, and Table VI provide detailed timing for the
digital interface of the ADS7846.
TABLE VI. Timing Specifications (+VCC = +2.7V and Above,
TA = –40°C to +85°C, CLOAD = 50pF).
CS
DCLK
1
8
1
8
1
8
1
DIN
BUSY
DOUT
S
S
Control Bits
Control Bits
11 10
9
8
7
6
5
4
3
2
1
0
11 10 9
FIGURE 10. Conversion Timing, 16 Clocks-per-Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated
serial port.
CS
tCL
tCSH
tCSS
tCH
tBD
tBD
tD0
DCLK
DIN
tDH
tDS
PD0
tBDV
tBTR
BUSY
DOUT
tDV
tTR
11
10
FIGURE 11. Detailed Timing Diagram.
ADS7846
14
SBAS125H
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