CS
RD
t1
t3
CLK
t12
t11
n – 1
BUSY
Conversion n
To prevent PWD
A0 must be 0
A0
t13
t14
n-1 DATA VALID
DB0-DB11
NOTE: Internal register of current conversion updated 1/2 clock cycle prior to BUSY going HIGH.
FIGURE 4. Read Timing Following a Conversion.
CS
t1
t2
t3
RD
CLK
t12
t11
BUSY
A0
t15
t16
NOTE: Rising edge of RD while A0 = 1 initiates power down immediately.
FIGURE 5. Entering Power-Down Using RD and A0.
CS
t1
t2
t3
RD
A0
t15
t16
NOTE: Rising edge of 2nd RD while A0 = 0 places the ADS7842 in sample mode.
FIGURE 6. Initiating Wake-Up Using RD and A0.
®
ADS7842
12