DIGITAL OUTPUT
STRAIGHT BINARY
CS
0
RD
WR BUSY A0
A1
X
COMMENTS
X
X
1
1
1
0
Power Down Mode
Wake Up Mode
DESCRIPTION
ANALOG INPUT
BINARY CODE
HEX CODE
0
X
Least Significant Bit (LSB)
Full Scale
1.2207mV
4.99878V
means rising edge triggered. X = Don't care.
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
FFF
800
7FF
000
Midscale
2.5V
2.49878V
0V
TABLE III. Truth Table for Power Down and Wake Up
Modes.
Midscale –1LSB
Zero Full Scale
Table IV. Ideal Input Voltages and Output Codes (VREF = 5V).
CS
Latching in Address for Next Channel
WR
Conversion
Sample
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
BUSY
RD
A0
A1
DB0-DB11
DATA VALID
FIGURE 2. Normal Operation, 16 Clocks per Conversion.
CS
t1
t3
t2
WR
t6
t8
t7
t4
CLK
tCKL
t5
BUSY
t10
t9
N + 1(1)
A0, A1
NOTE: (1) Addresses for next conversion (N + 1) latched in with rising edge of current WR (N).
FIGURE 3. Initiating a Conversion.
®
ADS7842
11
BB [ BURR-BROWN CORPORATION ]
