STARTING A CONVERSION
SYMBOL
DESCRIPTION
MIN TYP MAX UNITS
tCONV
tACQ
tCKP
tCKL
tCKH
t1
Conversion Time
Acquisition Time
3.5
1.5
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
A conversion is initiated on the falling edge of the WR input,
with valid signals on A0, A1, and CS. The ADS7842 will
enter the conversion mode on the first rising edge of the
external clock following the WR pin going LOW. The
ADS7842 will start the conversion on the 1st clock cycle. The
MSB will be approximated by the Capacitive Digital-to-
Analog Converter (CDAC) on the 1st clock cycle, the 2nd
MSB on the 2nd cycle, and so on until the LSB has been
decided on the 12th clock cycle. The BUSY output will go
LOW 20ns after the falling edge of the WR pin. The BUSY
output will return HIGH just after the ADS7842 has finished
a conversion and the data will be valid on pins 7 - 13, 15 - 19.
The rising edge of BUSY can be used to latch the data. It is
recommended that the data be read immediately after each
conversion. The switching noise of the asynchronous data
transfer can cause digital feedthrough degrading the
converter’s performance. See Figure 2.
Clock Period
300
150
150
0
Clock LOW
Clock HIGH
CS to WR/RD Setup Time
Address to CS Hold Time
CS LOW
t2
0
t3
25
25
t4
CLK to WR Setup Time
CS to BUSY LOW
CLK to WR LOW
CLK to WR HIGH
WR to CLK LOW
Address Hold Time
Address Setup Time
BUSY to RD Delay
CLK LOW to BUSY HIGH
BUS Access
t5
20
t6
5
25
25
5
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
5
0
10
25
25
2
BUS Relinquish
Address to RD HIGH
Address Hold Time
RD HIGH to CLK LOW
2
50
READING DATA
TABLE I. Timing Specifications (+VCC = +2.7V to 3.6V,
Data from the ADS7842 will appear at pins 7 - 13 and
15 - 19. The MSB will output on pin 7 while the LSB
will output on pin 19. The outputs are coded in Straight
Binary (with 0V = 000Hand VREF = FFFH, see Table IV).
Following a conversion, the BUSY pin will go HIGH.
After BUSY goes HIGH, the CS and RD pins may be
brought LOW to enable the 12-bit output bus. CS and
RD must be held LOW for at least 25ns seconds follow-
ing BUSY HIGH. Data will be valid 25ns seconds after
the falling edge of both CS and RD. The output data will
remain valid for 25ns seconds following the rising edge
of both CS and RD. See Figure 4 for the read cycle
timing diagram.
TA = –40°C to +85°C, CLOAD = 50pF).
SYMBOL
DESCRIPTION
MIN TYP MAX UNITS
tCONV
tACQ
tCKP
tCKL
tCKH
t1
Conversion Time
Acquisition Time
3.5
1.5
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock Period
300
150
150
0
Clock LOW
Clock HIGH
CS to WR/RD Setup Time
Address to CS Hold Time
CS LOW
t2
0
t3
25
25
t4
CLK to WR Setup Time
CS to BUSY LOW
CLK to WR LOW
CLK to WR HIGH
WR to CLK LOW
Address Hold Time
Address Setup Time
BUSY to RD Delay
CLK LOW to BUSY HIGH
BUS Access
t5
20
t6
5
25
25
5
t7
t8
POWER-DOWN MODE
t9
t10
t11
t12
t13
t14
t15
t16
t17
5
The ADS7842 incorporates a unique method of placing the
A/D in the power-down mode. Rather than adding an extra
pin to the package, the A0 address pin is used in conjunction
with the RD pin to place the device in power-down mode
and also to ‘wake-up’ the A/D following power-down. In
this shutdown mode, all analog and digital circuitry is turned
off. The simplest way to place the ADS7842 in power-down
mode is immediately following a conversion. After a con-
version has been completed and the BUSY output has
returned HIGH, CS and RD must be brought LOW for
minimum of 25ns. While keeping CS LOW, RD is brought
HIGH and the ADS7842 enters the power-down mode
provided the A0 pin is HIGH (see Figure 5 and Table III).
In order to ‘wake-up’ the device following power-down, A0
must be LOW when RD switches from LOW to HIGH a
second time (see Figure 6).
0
10
25
25
2
BUS Relinquish
Address to RD HIGH
Address Hold Time
RD HIGH to CLK LOW
2
50
TABLE II. Timing Specifications (+VCC = +4.75V to
+5.25V, TA = –40°C to +85°C, CLOAD = 50pF).
The typical supply current of the ADS7842 with a 5V supply
and 200kHz sampling rate is 550µA. In the power-down
mode the current is typically reduced to 3µA.
®
ADS7842
10
BB [ BURR-BROWN CORPORATION ]
