MICROPROCESSOR INTERFACE
While this is one of the most useful, the DSP56004/7 is
flexible enough to allow various other configurations. These
will free up the serial outputs for use with other serial
peripherals, such as DACs.
The internal logic of the ADS7833 is designed for easy
control and data interface with microprocessors. Figure 4
shows the interface for loading the input control word from
the microprocessor data bus into the serial input of the
ADS7833.
TYPICAL ISOLATED ANALOG INPUT
Table VIII provides a sample assembly code and Figure 4
shows the connection diagram for connecting an ADS7833
to the DSP56004N—or DSP56007 a Motorola Digital Sig-
nal Processor. This configuration allows for full control of
the ADS7833 as well as receiving all three conversion
results simultaneously. The start of conversion is generated
by the DSP56004 as well as the sample time of the asynchro-
nous sample/holds.
Figure 5 shows an ISO130 used to isolate the current
measurement in a motor speed control application. This
amplifier is well suited for this application because of its
high transient immunity (l0kV/µs). Its differential output
feature is well suited to the differential input of the ADS7833.
Keeping the signal transmission differential helps to pre-
serve the high frequency noise rejection of the system.
A unique characteristic of the ISO130 is that it has a common
mode output voltage of approximately 2.39V. To accept this
level of CMV, the ADS7833 must be operated at a gain of
5V/V (±0.5V full scale differential input). (See Figure 3 and
Table VII). Since the ISO130 has a gain of 8V/V, the
maximum value of VSENSE is 62.5mV. Thus, the value of
RSENSE is chosen to scale VSENSE to this maximum value.
DSP56004/7
SDO0
ADS7833
CONV
V1-1
V1-2
V1-3
SDO1
SOI0
SERIN
SOUT1
SOUT2
SOUT3
ASH
SOI1
POWER-UP INITIALIZATION
MOSI/HA0
MISO/NAU
SCKT
V2-1
V2-2
V2-3
(optional)
When power is applied to the ADS7833, two conversion
cycles are required for initialization and valid digital data is
transmitted on the third cycle.
CLK
SCKR
SCK/SCL
WST
V3-1
V3-2
V3-3
V3-4
The first conversion after power is applied is performed with
indeterminate configuration values in the double buffer
output of the Input Setup Register. The second conversion
cycle loads the desired values into the register. The third
conversion uses those values to perform proper conversions
and output valid digital data from each of the ADCs.
WSR
SS/HA2
SDO2
AOUT
FIGURE 4. Microprocessor Interface for Motorola
DSP56004/7.
movep
movep
movep
;
#>$0,x:$ffe4
#>$0,x:$ffe1
#>$0,x:$fff1
;
;
;
Disable SAI transmit port
Disable SAI receive port
Disable SHI port
movep
movep
movep
movep
movep
#>$dfff00,x:$ffe5
#>$101f00,x:$ffe6
#>$0,x:$ffe7
#>$10d,x:$ffe0
#>$3,x:$ffe1
;
;
;
;
;
Convert command
DAC to midscale, G=1V/V, Channel 1 all ADCs
For SS pin—enables SHI at proper time
Divide by 1 pre, divide by 13—96kHz conv @ 40MHz
Enable SAI recv (rsng edge, MSB 1st, 16-bits, slave)
movep
movep
movep
;
#>$2001,x:$fff0
#>$5,x:$fff1
#>$f,x:$ffe4
;
;
;
Set narrow spike filter, CPOL=0, CPHA=1
Enable SHI (slave, no fifo, 16-bits)
Enable SAI trans (rsng edge, MSB 1st, 16-bits, mstr)
wait
data
btst
jcs
btst
jcc
movep
move
movep
move
move
movep
#14,x:$ffe1
data
#15,x:$ffe1
wait
x:$ffe2,x0
x0,x:$00
x:$ffe3,x0
x0,x:$01
x:$fff3,x0
x0,x:$02
;
Look for a receive flag (left or right)
;
;
;
;
;
;
Get Sout1
Save it
Get Sout2
Save it
Get Sout3
Save it
TABLE VIII. Sample Code for Motorola DSP56004/7.
®
ADS7833
11
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