DAC OUTPUT VOLTAGE
As is common with most differential input semiconductor
devices, there are compound restrictions on the combination
of differential and common-mode input voltages. This mat-
ter is made slightly more complicated by the fact that most
of the analog inputs are capable of being affected by the
programmable gain function. The possible differential and
single ended configurations are shown in Figures 3a and 3b.
The value of the DAC output voltage is determined by the
DAC Input portion of the SERIN word (bits 0 through 7—see
Figure 2). The 8-bit DAC has 256 possible output voltages
from 0V to +2.49V. The value of 1 LSB is 0.0098V.
ANALOG-TO-DIGITAL
CONVERTERS
ARCHITECTURE
The maximum differential and common mode restrictions
are shown in Table VII.
GAIN SELECT CODE
0
1
2
3
The ADCs are 12-bit, successive approximation types imple-
mented with a switched capacitor circuitry.
Gain
5.0V/V
2.5V/V
1.25V/V
1.0V/V
Full Scale Range
(VD with VCM = 0)
±0.5V
+2.7V
–2.7V
±1.0V
+2.4V
–2.4V
±2.0V
+1.9V
–1.9V
±2.5V
+1.6V
–1.6V
SPEED
Largest Positive
Common Mode
The clock for the ADC conversion is supplied externally at
the CLK pin. Maximum clock frequency for specified accu-
racy is 2.1MHz. This results in a complete conversion cycle
(S/H acquisition and A/D conversion) of 6.6µs.
Voltage, VCM
+
Largest Negative
Common Mode
Voltage, VCM
–
TABLE VII. Differential and Common Mode Voltage
Restrictions.
INPUT/OUTPUT
The ADS7833 is designed for bipolar input voltages and
uses a binary two’s complement digital output code. A
programmable gain function is associated with each ADC.
This changes the full scale analog input range and the analog
resolution of the converter. Details are shown in Table VI.
(A)
V1 – 1 +
V1 – 1P
VD
2
+
VCM
VD
2
VCM
–
+
+
–
V1 – 1 –
DIFFERENTIAL AND COMMON-MODE
INPUT VOLTAGES
VD
2
VCM
The ADS7833 is designed with full differential signal paths
all the way from the multiplexer inputs through to the input
of the ADCs. This was done to provide superior high
frequency noise rejection.
VD
2
–
V1 – 1N
(B)
VD
V1 – 1
V1 – 1P
+
VD
VCM
DIGITAL INPUT
DAC INPUT0-7
ANALOG OUTPUT
–
+
HEX
CODE
BINARY
CODE
V1 – 1N
VCM
00H
0000 0000
0V
01H
•
0000 0001
+0.0098V
–
•
•
•
•
•
•
•
•
FFH
1111 1111
+2.499
FIGURE 3. (a) Differential Signal Source, and (b) Single
Ended Signal Source.
TABLE V. DAC Input/Output Relationships.
DESCRIPTION
ANALOG INPUT
DIGITAL OUTPUT
GAIN SELECT CODE
GAIN
0
1
2
3
5V/V
±0.5V
2.5V/V
1.25V/V
±2.0V
1.0V/V
BINARY TWO’S COMPLIMENT FORMAT
FULL SCALE RANGE
±1.0V
±2.5V
HEX CODE
BINARY CODE
+Full Scale (FS –1LSB)
One Bit above Mid-Scale
Mid-Scale
One Bit Below Mid-Scale
–Full Scale
+0.49976
+0.244mV
0V
–0.244V
–0.500V
+0.9995V
+0.488mV
0V
–0.488mV
–1.000V
+1.999V
+0.976mV
0V
–0.976mV
–2.000V
+2.499
+1.22mV
0V
–1.22mV
–2.500V
7FFH
001H
000H
FFFH
800H
0111 1111 1111
0000 0000 0001
0000 0000 0000
1111 1111 1111
1000 0000 0000
NOTE: The programmable gain function applies to all three input channels for ADC1 and ADC2. However, the programmable gain function only applies to the
first input (V3-1) for ADC3. The other three inputs (V3-2, V3-3, and V3-4) are not affected by the GAIN SEL input. They operate at a fixed gain of 1V/V and thus
have a fixed ±2.5V full scale input range.
TABLE VI. Analog Input - Digital Output Relationships.
®
ADS7833
10
BB [ BURR-BROWN CORPORATION ]
