THEORY OF OPERATION
+5V
ADS7832 uses the advantages of advanced CMOS technol-
ogy (logic density, stable capacitors, precision analog
switches, and low power consumption) to provide a precise
12-bit analog-to-digital converter with on-chip sampling and
four-channel analog-input multiplexer.
NC
1
2
3
4
5
6
7
8
9
SFR
AIN0
AIN1
AIN2
AIN3
VA
28
+
10nF
AGND 27
CAL 26
A1 25
10µF
0 –5V
Input
NC
100kΩ
A0 24
The input stage consists of an analog multiplexer with an
address latch to select from four input channels.
+5V
VREF+
CLK 23
BUSY 22
HBE 21
WR 20
CS 19
10nF
+
BUSY
VREF–
10µF
The converter stage consists of an advanced successive
approximation architecture using charge redistribution on a
capacitor network to digitize the input signal. A tempera-
ture-stabilized differential auto-zeroing circuit is used to
minimize offset errors in the comparator.
High Byte
Enable
Command
DGND
VD
Convert
Command
BUSY
LOW
LOW
LOW
Data Bit 7 10 D7
Data Bit 6 11 D6
Data Bit 5 12 D5
Data Bit 4 13 D4
Read Command
RD 18
Linearity errors in the binary weighted main capacitor
network are corrected using a capacitor trim network and
correction factors stored in on-chip memory. The correction
terms are calculated by an on-chip microcontroller during a
calibration cycle, initiated either by power-up or by applying
an external calibration signal at any time. During conver-
sion, the correct trim capacitors are switched into the main
capacitor array as needed to correct the conversion accuracy.
With all of the capacitors in both the main array and the trim
array on the same chip, excellent stability is achieved, both
over temperature and over time.
D0 17 Data Bit 0 Data Bit 8
(LSB)
D1 16 Data Bit 1 Data Bit 9
Data Bit 11 Data Bit 3 14 D3
(MSB)
D2 15 Data Bit 2 Data Bit 10
HBE Input HBE Input
HBE Input HBE Input
HIGH
LOW
LOW
HIGH
FIGURE 1. Basic Operation.
approximation conversion takes place during clock cycles 6
through 17.
For flexibility, timing circuits include both an internal clock
generator and an input for an external clock to synchronize
with external systems. Standard control signals and three-
state input/output registers simplify interfacing ADS7832 to
most micro-controllers, microprocessors or digital storage
systems.
Figures 2 and 3 show the full conversion sequence and the
timing to initiate a conversion.
A conversion can also be initiated by a rising edge on pin 26,
if a HIGH has been written to D2 of the Special Function
Register, as discussed below.
The on-chip sampling provides excellent dynamic perfor-
mance for input signals to 50kHz, and has a full-power –3dB
bandwidth of 4MHz. Full control over sample-to-hold
timing is available for applications where this is critical.
CALIBRATION
A calibration cycle is initiated automatically upon power-up
(or after a power failure). Calibration can also be initiated by
the user at any time by the rising edge of a minimum 100ns-
wide LOW pulse on the CAL pin (pin 26), or by setting D1
HIGH in the Special Function Register (see SFR section).
A calibration command will initiate a calibration cycle,
regardless of whether a conversion is in process. During a
calibration cycle, convert commands are ignored.
Finally, this performance is matched with the low-power
advantages of CMOS structures to allow a typical power
consumption of 10mW, with a 50µW power down option.
OPERATION
BASIC OPERATION
Calibration takes 4608 clock cycles, and a normal conver-
sion (17 clock cycles) is added automatically. Thus, at the
end of a calibration cycle, there is valid conversion data in
the output registers. For maximum accuracy, the supplies
and reference need to be stable during the calibration proce-
dure. To ensure that supply voltages have settled and are
stable, an internal timer provides a waiting period of 37,393
clock cycles between power-up/power-failure and the start
of the calibration cycle.
Figure 1 shows the simple circuit required to operate
ADS7832 in the Transparent Mode, converting a single
input channel. A convert command on pin 20 (WR) starts a
conversion. Pin 22 (BUSY) will output a LOW during the
conversion process (including sample acquisition and con-
version), and rises only after the conversion is completed.
The two bytes of output data can then be read using pin 18
(RD) and pin 21 (HBE).
STARTING A CONVERSION
READING DATA
A conversion is initiated on the rising edge of the WR input,
with valid signals on A0, A1 and CS. The selected input
channel is sampled for five clock cycles. The successive
Data from the ADS7832 is read in two 8-bit bytes, with the
Low byte containing the 8 LSBs of data, and the High byte
containing the 4 MSBs of data. The outputs are coded in
®
8
ADS7832
BB [ BURR-BROWN CORPORATION ]
