PIN ASSIGNMENTS
PIN #
NAME
DESCRIPTION
1
SFR
Special Function Register. When connected to a microprocessor address pin, allows access to special functions
through D0 to D7. If not used, connect to DGND. This pin has an internal pull-down.
2 to 5
AIN0 to AIN3
Analog inputs. Channel 0 to channel 3.
6
VREF
+
–
Positive voltage reference input. Must be ≤ (VA + 0.3V).
Negative voltage reference input.
7
VREF
8
9
DGND
VD
Digital ground. DGND = 0V.
Logic supply voltage. Must be ≤ (VA + 0.3V) and applied after VA.
10 to 17
D0 to D7
Data Bus Input/Output Pins. Normally used to read output data.
When SFR is LOW, these function as follows:
10
D7
Data Bit 7 if HBE is LOW; if HBE is HIGH, acts as converter status pin and is HIGH during conversion or calibration,
goes LOW after the conversion is completed. (Acts as an inverted BUSY).
Data Bit 6 if HBE is LOW; LOW if HBE is HIGH.
Data Bit 5 if HBE is LOW; LOW if HBE is HIGH.
Data Bit 4 if HBE is LOW; LOW if HBE is HIGH.
Data Bit 3 if HBE is LOW; Data Bit 11 (MSB) if HBE is HIGH.
Data Bit 2 if HBE is LOW; Data Bit 10 if HBE is HIGH.
Data Bit 1 if HBE is LOW; Data Bit 9 if HBE is HIGH.
11
12
13
14
15
16
17
D6
D5
D4
D3
D2
D1
D0
Data Bit 0 (LSB) if HBE is LOW; Data Bit 8 if HBE is HIGH.
18
19
20
RD
CS
Read Input. Active LOW; used to read the data outputs in combination with CS and HBE.
Chip Select Input. Active LOW.
WR
Write Input. Active LOW; used to start a new conversion and to select an analog channel via address inputs A0 and A1
in combination with CS. The minimum WR pulse LOW width is 100ns.
21
22
23
HBE
BUSY
CLK
High Byte Enable. Used to select high or low data output byte in combination with CS and RD, or to select SFR.
BUSY is LOW during conversion or calibration. BUSY goes HIGH after the conversion is completed.
Clock Input. For internal or external clock operation. For external clock operation, connect to a 74HC-compatible
clock source. For internal clock operation, connect per the clock operation description.
24 to 25
A0 to A1
Address Inputs. Used to select one of four analog input channels in combination with CS and WR. The address inputs
are latched on the rising edge of WR or CS.
A1
A0
Selected Channel
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
AIN0
AIN1
AIN2
AIN3
26
CAL
(SHC)
Calibration Input. A calibration cycle is initiated when CAL is LOW. The minimum pulse width of CAL is 100ns. If not
used, connect to VD. In this case calibration is only initiated at power on, or with SFR. If D2 of the SFR is programmed
HIGH, pin 26 will be an input to control the sample-to-hold timing. A rising edge on pin 26 will switch from sample-mode
to hold-mode and initiate a conversion. This pin has an internal pull-up.
27
28
AGND
VA
Analog Ground. AGND = 0V.
Analog Supply. Must be ≥ (VD – 0.3V) and ((VREF +) – 0.3V)
®
7
ADS7832
BB [ BURR-BROWN CORPORATION ]
