SPECIFICATIONS
ADS7832 Electrical Specifications with 5V Supply
VA = VD = 5V ±10%; VREF+ = 5.0V; VREF– = AGND = DGND = 0V; CLK = 1MHz external 50% ±2% Duty Cycle, TA = –40°C to +85°C, after calibration at any temperature,
unless otherwise specified.
ADS7832BP/ADS7832BN
PARAMETER
RESOLUTION
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
ANALOG INPUT
Voltage Input Range
Input Capacitance
V
D = VA = VREF+ = 5V
0
5
V
pF
40
On State Bias Current
Off State Bias Current
100
10
100
nA
nA
nA
Ω
MΩ
LSB
T
A = +25°C
T
A = –40°C to +85°C
On Resistance Multiplexer
Off Resistance Multiplexer
Channel Separation
400
10
0.5
F
IN = 1kHz, VD = VA = VREF+ = 5V
VREF = VA = 5V
REFERENCE INPUT
For Specified Performance:
VREF
VREF
+
–
VA
0
V
V
For Derated Performance(2)
:
(VREF+) – (VREF–) ≥ 2.5V
VREF
VREF
+
–
2.5
0
VA
1
V
V
Input Reference Current
100
200
µA
THROUGHPUT SPEED
Conversion Time With External Clock (Including
Multiplexer Settling Time and Acquisition Time)
CLK = 2MHz
CLK = 1MHz
CLK = 500kHz
8.5
17
34
µs
µs
µs
With Internal Clock Using Recommended
Clock Components
T
A = +25°C
30
30
µs
µs
T
A = –40°C to +85°C
Slew Rate
Multiplexer Settling Time to 1/2 LSB
Multiplexer Access Time
2
mV/µs
µs
ns
0.5
20
SAMPLING DYNAMICS
Full Power Bandwidth
Aperture Jitter
–3dB
4
10
2.5
5
MHz
ps
µs
Aperture Delay
SRF D2 LOW(3)
SFR D2 HIGH
ns
DC ACCURACY
Integral Nonlinearity, All Channels
SFR D2 LOW
±0.75
LSB(4)
LSB
SFR D2 HIGH, Internal Clock or Sampling
Command Synchronous to External Clock
SFR D2 HIGH, Sampling
±0.5
±0.6
LSB
LSB
Command Asynchronous to External Clock
Differential Nonlinearity
No Missing Codes
Gain Error
±0.75
±0.50
Guaranteed
All Channels
LSB
Gain Error Drift
Offset Error
Between Calibration Cycles
±0.2
ppm/°C
All Channels
SFR D2 LOW
±0.75
LSB
LSB
SFR D2 HIGH, Internal Clock or Sampling
Command Synchronous to External Clock
SFR D2 HIGH, Sampling
±1
±4
LSB
Command Asynchronous to External Clock
Between Calibration Cycles
Offset Error Drift
SFR D2 LOW
±0.2
±0.5
ppm/°C
ppm/°C
SFR D2 HIGH, Internal Clock or Sampling
Command Synchronous to External Clock
SFR D2 HIGH, Sampling
±1
ppm/°C
Command Asynchronous to External Clock
SFR D2 LOW
SFR D2 HIGH, Internal Clock or Sampling
Command Synchronous to External Clock
SFR D2 HIGH, Sampling
Channel-to-Channel Mismatch
Power Supply Sensitivity
±0.25
±0.5
LSB
LSB
±1.0
LSB
LSB
Command Asynchronous to External Clock
V
D = VA = +5V ±10% (without recalibration)
±0.125
®
4
ADS7832
BB [ BURR-BROWN CORPORATION ]
