5V
ADS7832
Test
Output
Point
3kΩ
3kΩ
CL
ADS7832
Test
Output
Point
CL
(a) Load Circuit
(a) Load Circuit
tFALL
tFALL
VD
Output
Enable
90%
50%
VD
Output
Enable
90%
50%
10%
Gnd
VOH
Gnd
10%
Gnd
VD
90%
10%
t15
t14
VOL
t15
t14
(b) From HIGH to Hi-Z, CL = 10pF
(b) From LOW to Hi-Z, CL = 10pF
tRISE
VD
tRISE
Output
Enable
90%
50%
10%
VD
Output
Enable
90%
50%
10%
Gnd
VOH
Gnd
VD
t13
t13
2.4V
Gnd
0.8V
VOL
(c) From Hi-Z to HIGH, CL = 100pF
(c) From Hi-Z to LOW, CL = 100pF
FIGURE 8. Measuring Active LOW to/from Hi-Z State.
As long as there is at least a 4.5V difference between VREF
and VREF–, the absolute value of errors does not change
significantly, so that accuracy will typically be within ±1LSB
FIGURE 9. Measuring Active HIGH to/from Hi-Z State.
+
This is also a good method to further isolate the ADS7832
from digital supplies in a system with significant switching
currents that could degrade the accuracy of conversions.
The power supply to the reference source needs to be
considered during system design to prevent VREF+ from
exceeding (or overshooting) VA, particularly at power-on.
Also, after power-on, if the reference is not stable within
33,056 clock cycles, an additional calibration cycle may be
needed.
GROUNDING
To maximize accuracy of the ADS7832, the analog and
digital grounds are not connected internally. These points
should have very low impedance to avoid digital noise
feeding back into the analog ground. The VREF– pin is used
as the reference point for input signals, so it should be
connected directly to AGND to reduce potential noise prob-
lems.
POWER SUPPLIES
The digital and analog power supply lines to the ADS7832
should be bypassed with 10µF tantalum capacitors as close
to the part as possible. Although ADS7832 has excellent
power supply rejection, even for higher frequencies, linear
regulated power supplies are recommended.
EXTERNAL CLOCK OPERATION
The circuitry required to drive the ADS7832 clock from an
external source is shown in Figure 12a. The external clock
must provide a 0.8V max for LOW and a 3.5V min for
HIGH, with rise and fall times that do not exceed 200ns. The
duty cycle of the external clock can vary as long as the LOW
time and HIGH time are each at least 200ns wide. Synchro-
nizing the conversion clock to an external system clock is
Care should be taken to insure that VD does not come up
before VA, or permanent damage to the part may occur.
Figure 11 shows a good supply approach, powering both VA
and VD from a clean linear supply, with the 10Ω resistor
between VA and VD insuring that VD comes up after VA.
®
13
ADS7832
BB [ BURR-BROWN CORPORATION ]
