CONTROL LINES
full power bandwidth of the system. For higher source
impedances, a buffer like the one in Figure 10b should be
used.
Table IV shows the functions of the various control lines on
the ADS7832. The use of standard CS, RD and WR control
signals simplifies use with most microprocessors. At the
same time, flexibility is assured by availability of status
information and control functions, both through the SFR and
directly on pins.
INPUT PROTECTION
The input signal range must not exceed ±VREF or VA by
more than 0.3V.
The analog inputs are internally clamped to VA. To prevent
damage to the ADS7832, the current that can flow into the
inputs must be limited to 20mA. One approach is to use an
external resistor in series with the input filter resistor. For
example, a 1kΩ input resistor allows an overvoltage to 20V
without damage.
INSTALLATION
INPUT IMPEDANCE
ADS7832 has a very high input impedance (input bias
current over temperature is 100nA max), and a low 50pF
input capacitance. To ensure a conversion accurate to 12
bits, the analog source must be able to charge the 50pF and
settle within the first five clock cycles after a conversion is
initiated. During this time, the input is also very sensitive to
noise at the analog input, since it could be injected into the
capacitor array.
REFERENCE INPUTS
A 10µF tantalum capacitor is recommended between VREF
+
and VREF– to insure low source impedance. These capaci-
tors should be located as close as possible to the ADS7832
to reduce dynamic errors, since the reference provides pack-
ets of current as the successive approximation steps are
carried out.
In many applications, a simple passive low-pass filter as
shown in Figure 10a can be used to improve signal quality.
In this case, the source impedance needs to be less than 5kΩ
to keep the induced offset errors below 1/2LSB, and to meet
the acquisition time of five clock cycles. The values in
Figure 10a meet these requirements, and will maintain the
VREF+ must not exceed VA. Although the accuracy is speci-
fied with VREF+ = 5V and VREF– = 0V, the converter can
function with VREF+ as low as 4.5V and VREF– as high as
1V.
CS
RD
WR
SFR
HBE
CAL
BUSY
OPERATION
X
X
X
X
X
0↑ 1
X
Initiates calibration cycle. (See SFR section for alternate use as Sample/
Hold Control Mode input.)
X
1
0
0
0
0
0
0
0
X
X
1
0
0
1
0
1
0
X
X
X
X
0
0
0
1
1
1
1
X
X
X
0
1
1
1
0
0
X
1
1
1
1
1
1
1
1
0
X
1
Conversion or calibration in process. Inhibits new conversion from starting.
None. Outputs in Hi-Z State.
0↑1
1
Initiates conversion.
X
X
1
Low byte conversion results output on data bus.
High byte conversion results output on data bus.
Write to SFR and rising edge on WR initiates conversion.
Contents of SFR output on data bus.
1
0
1
X
X
X
0
Reserved for factory use.
1
Reserved for factory use. (Unpredictable data on data bus.)
TABLE IV. Control Line Functions.
1
2
11
12
CLK
t18
SHC
(Pin 26)
t20
BUSY
t19
Sample
Hold
Convert
Sample
FIGURE 7. Timing for Initiating Conversion in Sample/Hold Control Mode (D2 in SFR HIGH).
®
12
ADS7832
BB [ BURR-BROWN CORPORATION ]
