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ADS7806U 参数 Datasheet PDF下载

ADS7806U图片预览
型号: ADS7806U
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗,12位采样CMOS模拟数字转换器 [Low-Power 12-Bit Sampling CMOS ANALOG-to-DIGITAL CONVERTER]
分类和应用: 转换器
文件页数/大小: 18 页 / 211 K
品牌: BB [ BURR-BROWN CORPORATION ]
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The ADS7806 will begin tracking the input signal at the end  
of the conversion. Allowing 25µs between convert com-  
mands assures accurate acquisition of a new signal. Refer to  
Tables III and IV for a summary of CS, R/C, and BUSY  
states and Figures 2 through 6 for timing diagrams.  
CS and R/C are internally OR’d and level triggered. There  
is not a requirement which input goes LOW first when  
initiating a conversion. If, however, it is critical that CS or  
R/C initiates conversion ‘n’, be sure the less critical input is  
LOW at least 10ns prior to the initiating input. If EXT/INT  
(pin 8) is LOW when initiating conversion ‘n’, serial data  
from conversion ‘n-1’ will be output on SDATA (pin 19)  
following the start of conversion ‘n’. See Internal Data  
Clock in the Reading Data section.  
CS  
1
R/C BUSY OPERATION  
X
0
X
1
None. Databus is in Hi-Z state.  
Initiates conversion “n”. Databus remains  
in Hi-Z state.  
To reduce the number of control pins, CS can be tied LOW  
using R/C to control the read and convert modes. This will  
have no effect when using the internal data clock in the serial  
output mode. However, the parallel output and the serial  
output (only when using an external data clock) will be  
affected whenever R/C goes HIGH. Refer to the Reading  
Data section.  
0
0
0
0
1
1
1
0
1
1
0
0
Initiates conversion “n”. Databus enters Hi-Z  
state.  
Conversion “n” completed. Valid data from  
conversion “n” on the databus.  
Enables databus with valid data from  
conversion “n”.  
Enables databus with valid data from  
conversion “n-1”(1). Conversion n in progress.  
Enables databus with valid data from  
conversion “n-1”(1). Conversion “n” in progress.  
READING DATA  
The ADS7806 outputs serial or parallel data in Straight  
Binary or Binary Two’s Complement data output format. If  
SB/BTC (pin 7) is HIGH, the output will be in SB format,  
and if LOW, the output will be in BTC format. Refer to  
Table V for ideal output codes.  
New conversion initiated without acquisition  
of a new signal. Data will be invalid. CS and/or  
R/C must be HIGH when BUSY goes HIGH.  
X
X
0
New convert commands ignored. Conversion  
“n” in progress.  
NOTE: (1) See Figures 2 and 3 for constraints on data valid from  
conversion “n-1”.  
The parallel output can be read without affecting the internal  
output registers; however, reading the data through the serial  
Table III. Control Functions When Using Parallel Output  
(DATACLK tied LOW, EXT/INT tied HIGH).  
CS  
R/C  
0
BUSY  
EXT/INT  
DATACLK  
Output  
Output  
Input  
OPERATION  
1
1
1
1
1
0
0
1
1
1
Initiates conversion “n”. Valid data from conversion “n-1” clocked out on SDATA.  
Initiates conversion “n”. Valid data from conversion “n-1” clocked out on SDATA.  
Initiates conversion “n”. Internal clock still runs conversion process.  
Initiates conversion “n”. Internal clock still runs conversion process.  
0
0
0
Input  
1
Input  
Conversion “n” completed. Valid data from conversion “n” clocked out on SDATA synchronized  
to external data clock.  
0
0
X
1
0
0
0
1
1
Input  
Input  
X
Valid data from conversion “n-1” output on SDATA synchronized to external data clock.  
Conversion “n” in progress.  
Valid data from conversion “n-1” output on SDATA synchronized to external data clock.  
Conversion “n” in progress.  
0
X
X
X
New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C  
must be HIGH when BUSY goes HIGH.  
X
New convert commands ignored. Conversion “n” in progress.  
NOTE: (1) See Figures 4, 5, and 6 for constraints on data valid from conversion “n-1”.  
Table IV. Control Functions When Using Serial Output.  
DIGITAL OUTPUT  
DESCRIPTION  
ANALOG INPUT  
BINARY TWO’S COMPLEMENT  
STRAIGHT BINARY  
(SB/BTC HIGH)  
Full-Scale Range  
±10  
0V to 5V  
1.22mV  
0V to 4V  
(SB/BTC LOW)  
Least Significant Bit (LSB)  
4.88mV  
976µV  
HEX  
CODE  
7FF  
HEX  
CODE  
FFF  
BINARY CODE  
BINARY CODE  
+Full Scale (FS – 1LSB)  
Midscale  
9.99512V  
0V  
4.99878V  
2.5V  
3.999024V  
2V  
0111 1111 1111 1111  
0000 0000 0000 0000  
1111 1111 1111 1111  
1000 0000 0000 0000  
1111 1111 1111 1111  
1000 0000 0000 0000  
0111 1111 1111 1111  
0000 0000 0000 0000  
000  
800  
One LSB Below Midscale  
–Full Scale  
–4.88mV  
–10V  
2.49878V  
0V  
1.999024V  
0V  
FFF  
7FF  
800  
000  
Table V. Output Codes and Ideal Input Voltages.  
®
ADS7806  
8