Binary (BIN) Output
Analog Input Voltage Range
One Least Significant Bit
(LSB)
Defined As:
FSR
2
n
n=8
n = 12
+ Full-Scale Calibration
Midscale Calibration (Bipolar Offset)
Zero Calibration ( – Full-Scale Calibration)
±10V
20V
2
n
78.13mV
4.88mV
+10V – 3/2LSB
0V – 1/2LSB
–10V + 1/2LSB
Input Voltage Range and LSB Values
±5V
10V
2
n
39.06mV
2.44mV
+5V – 3/2LSB
0V – 1/2LSB
–5V + 1/2LSB
0V to +10V
10V
2
n
39.06mV
2.44mV
+10V – 3/2LSB
+5V – 1/2LSB
0V +1/2LSB
0V to +20V
20V
2
n
78.13mV
4.88mV
+20V – 3/2LSB
+10V – 1/2LSB
0V +1/2LSB
Output Transition Values
FFE
H
to FFF
H
7FFF
H
to 800
H
000
H
to 001
H
TABLE I. Input Voltages, Transition Values, and LSB Values.
DESIGNATION
CE (Pin 6)
CS (Pin 3)
R/C (Pin 5)
DEFINITION
Chip Enable
(active high)
Chip Select
(active low)
Read/Convert
(“1” = read)
(“0” = convert)
Byte Address
Short Cycle
Data Mode Select
(“1” = 12 bits)
(“0” = 8 bits)
FUNCTION
Must be HIGH (“1”) to either initiate a conversion or read output data. 0-1 edge may be used to initiate a
conversion.
Must be LOW (“0”) to either initiate a conversion or read output data. 1-0 edge may be used to initiate a
conversion.
Must be LOW (“0”) to initiate either 8- or 12-bit conversions. 1-0 edge may be used to initiate a conversion.
Must be HIGH (“1”) to read output data. 0-1 edge may be used to initiate a read operation.
In the start-convert mode, A
O
selects 8-bit (A
O
= “1”) or 12-bit (A
O
= “0”) conversion mode. When reading
output data in two 8-bit bytes, A
O
= “0” accesses 8 MSBs (high byte) and A
O
= “1” accesses 4 LSBs and
trailing “0s” (low byte).
When reading output data, 12/8 = “1” enables all 12 output bits simultaneously. 12/8 = “0” will enable the
MSBs or LSBs as determined by the A
O
line.
A
O
(Pin 4)
12/8 (Pin 2)
TABLE II. Control Line Functions.
CE
0
X
↑
↑
1
1
1
1
1
1
1
CS
X
1
0
0
↓
↓
0
0
0
0
0
R/C
X
X
0
0
0
0
↓
↓
1
1
1
12/8
X
X
X
X
X
X
X
X
1
0
0
A
O
X
X
0
1
0
1
0
1
X
0
1
OPERATION
None
None
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Enable 12-bit output
Enable 8 MSBs only
Enable 4 LSBs plus 4
trailing zeroes
TABLE III. Control Input Truth Table.
READING OUTPUT DATA
After conversion is initiated, the output data buffers remain
in a high-impedance state until the following four logic
conditions are simultaneously met: R/C HIGH, STATUS
LOW, CE HIGH, and CS LOW. Upon satisfaction of these
conditions the data lines are enabled according to the state of
inputs 12/8 and A
0
. See Figure 6 and Table V for timing
relationships and specifications.
In most applications the 12/8 input will be hard-wired in
either the HIGH or LOW condition, although it is fully TTL
and CMOS-compatible and may be actively driven if de-
sired. When 12/8 is HIGH, all 12 output lines (DB0-DB11)
are enabled simultaneously for full data word transfer to a
12-bit or 16-bit bus. In this situation the A
0
state is ignored
when reading the data.
When 12/8 is LOW, the data is presented in the form of two
8-bit bytes, with selection of the byte of interest accom-
plished by the state of A
0
during the read cycle. When A
0
is
LOW, the byte addressed contains the 8MSBs. When A
0
is
HIGH, the byte addressed contains the 4LSBs from the
conversion followed by four logic zeros which have been
forced by the control logic. The left-justified formats of the
two 8-bit bytes are shown in Figure 7. Connection of the
ADS774 to an 8-bit bus for transfer of the data is illustrated
in Figure 8. The design of the ADS774 guarantees that the
A
0
input may be toggled at any time with no damage to the
converter; the outputs which are tied together in Figure 8
cannot be enabled at the same time. The A
0
input is usually
driven by the least significant bit of the address bus, allow-
ing storage of the output data word in two consecutive
memory locations.
®
ADS774
8
BURR-BROWN [ BURR-BROWN CORPORATION ]
