+5V
10µF
1
2
3
4
28
27 DB11 (MSB)
26 DB10
25 DB9
24 DB8
23 DB7
ADS774
22 DB6
21 DB5
20 DB4
19 DB3
18 DB2
17 DB1
16 DB0 (LSB)
15
Status
Output
Convert Command
5
+5V
NC*
6
7
8
50Ω
(1)
9
10
50Ω
11
12
Leave Unconnected 13
14
±10V
Analog
Input
*Not internally connected
NOTE: (1) Connect to GND or V
EE
for
Emulation Mode. Connect to +5V for
Control Mode.
FIGURE 2. Basic
±10V
Operation.
presented as 12-bit words. The stand-alone mode is used in
systems containing dedicated input ports which do not
require full bus interface capability.
Conversion is initiated by a HIGH-to-LOW transition of
R/C. The three-state data output buffers are enabled when
R/C is HIGH and STATUS is LOW. Thus, there are two
possible modes of operation; data can be read with either a
positive pulse on R/C, or a negative pulse on STATUS. In
either case the R/C pulse must remain LOW for a minimum
of 25ns.
Figure 3 illustrates timing with an R/C pulse which goes
LOW and returns HIGH during the conversion. In this case,
the three-state outputs go to the high-impedance state in
response to the falling edge of R/C and are enabled for
external access of the data after completion of the conver-
sion.
Figure 4 illustrates the timing when a positive R/C pulse is
used. In this mode the output data from the previous conver-
sion is enabled during the time R/C is HIGH. A new
conversion is started on the falling edge of R/C, and the
three-state outputs return to the high-impedance state until
the next occurrence of a HIGH R/C pulse. Timing specifica-
tions for stand-alone operation are listed in Table IV.
FULLY CONTROLLED OPERATION
Conversion Length
Conversion length (8-bit or 12-bit) is determined by the state
of the A
0
input, which is latched upon receipt of a conver-
sion start transition (described below). If A
0
is latched
HIGH, the conversion continues for 8 bits. The full 12-bit
conversion will occur if A
0
is LOW. If all 12 bits are read
7
following an 8-bit conversion, the 4LSBs (DB0-DB3) will
be LOW (logic 0). A
0
is latched because it is also involved
in enabling the output buffers. No other control inputs are
latched.
CONVERSION START
The converter initiates a conversion based on a transition
occurring on any of three logic inputs (CE, CS, and R/C) as
shown in Table III. Conversion is initiated by the last of the
three to reach the required state and thus all three may be
dynamically controlled. If necessary, all three may change
state simultaneously, and the nominal delay time is the same
regardless of which input actually starts the conversion. If it
is desired that a particular input establish the actual start of
conversion, the other two should be stable a minimum of
50ns prior to the transition of the critical input. Timing
relationships for start of conversion timing are illustrated in
Figure 5. The specifications for timing are contained in
Table V.
The STATUS output indicates the current state of the con-
verter by being in a high state only during conversion.
During this time the three state output buffers remain in a
high-impedance state, and therefore data cannot be read
during conversion. During this period additional transitions
of the three digital inputs which control conversion will be
ignored, so that conversion cannot be prematurely termi-
nated or restarted. However, if A
0
changes state after the
beginning of conversion, any additional start conversion
transition will latch the new state of A
0
, possibly resulting in
an incorrect conversion length (8 bits vs 12 bits) for that
conversion.
®
ADS774
BURR-BROWN [ BURR-BROWN CORPORATION ]
